Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information

• US 7,478,031 B2
• Filed: 11/07/2002
• Issued: 01/13/2009
• Est. Priority Date: 11/07/2002
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: QST Holdings LLC
• Inventors: Master, Paul L., Wu, Bicheng William, Hogenauer, Eugene, Chuang, Dan MingLun, Freeman-Benson, Bjorn
• Primary Examiner(s): Rodriguez, Paul L
• Assistant Examiner(s): Thangavelu, Kandasamy
• Application Number:
  US10/289,639
• Publication Number:
  US 20040093601A1
• Time in Patent Office: 2,259 Days
• Field of Search: 703 13- 15, 703/22, 717/119, 717/159, 717/160, 717/136, 713/100, 713/189, 709/220, 709/328, 375/148, 712/28, 712/29, 712/227
• US Class Current: 703/22
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit. The exemplary system includes a scheduler, a memory, and a compiler. The scheduler is capable of scheduling a selected algorithm with a plurality of adaptive computing descriptive objects to produce a scheduled algorithm and a selected adaptive computing circuit version. The memory is utilized to store the plurality of adaptive computing descriptive objects and a plurality of adaptive computing circuit versions generated during the scheduling process. The selected adaptive computing circuit version is converted into a hardware description language, for fabrication into the adaptive computing integrated circuit. The compiler generates the configuration information, from the scheduled algorithm and the selected adaptive computing circuit version, for the performance of the algorithm by the adaptive computing integrated circuit. In the exemplary embodiments, multiple versions of configuration information may be generated, for different circuit versions, different feature sets, different operating conditions, and different operating modes.

Claims

1. A computer implemented method for development of configuration information for an adaptive computing integrated circuit that includes a plurality of heterogeneous computing elements, the plurality of heterogeneous computing elements adapted to being coupled to each other by a reconfigurable interconnection network, the configuration information configuring or reconfiguring the interconnection network to interconnect one or more of the plurality of the heterogeneous computing elements to perform at least a part of an algorithm, the method comprising:

(a) selecting the algorithm for performance by the adaptive computing integrated circuit;

(b) determining, using a computing system, a plurality of adaptive computing descriptive objects for functions of the selected algorithm;

(c) scheduling, using the computing system, the selected algorithm with the plurality of adaptive computing descriptive objects to produce a scheduled algorithm; and

(d) from the scheduled algorithm and the plurality of adaptive computing descriptive objects, generating, using the computing system, the configuration information for the performance of the algorithm by the adaptive computing integrated circuit, the configuration information used to configure or reconfigure the interconnection network to interconnect the one or more of the plurality of the heterogeneous computing elements to perform the at least part of the algorithm, each of the one or more of the plurality of the heterogeneous computing elements performing a corresponding computational task of the at least part of the algorithm.

2. The method of claim 1, further comprising:

converting the adaptive computing descriptive objects to a hardware description language file for use in the fabrication of a fixed architecture, computing integrated circuit.

3. The method of claim 1, further comprising selecting the adaptive computing integrated circuit by:

generating, using the computing system, a plurality of adaptive computing circuit versions from the plurality of adaptive computing descriptive objects;

scheduling, using the computing system, the algorithm with the plurality of adaptive computing descriptive objects of each of the plurality of adaptive computing circuit versions; and

using a circuit version selection parameter of a plurality of circuit version selection parameters, selecting, using the computing system, an adaptive computing circuit version from the plurality of adaptive computing circuit versions, the selected adaptive computing circuit version corresponding to the selected adaptive computing integrated circuit.

4. The method of claim 3, wherein the plurality of circuit version selection parameters comprises at least two of the following circuit version selection parameters:

power consumption, speed of operation, latency, bandwidth requirements, a competing operating mode, and versatility for a plurality of operating modes.

5. The method of claim 1, wherein step (a) further comprises:

profiling, using the computing system, the algorithm for performance on the one or more heterogeneous computing elements of the adaptive computing integrated circuit.

6. The method of claim 5, wherein the profiling is based upon a plurality of data parameters, the plurality of data parameters comprising at least two of the following parameters:

data location for static data;

data type, input data size;

output data size;

data source location;

data destination location;

data pipeline length;

locality of reference;

distance of data movement;

speed of data movement;

data access frequency;

number of data load/stores;

cache usage;

register usage;

memory usage, and data persistence.

7. The method of claim 1, further comprising:

compiling, using the computing system, the configuration information into an adaptive computing integrated circuit bit file.

8. The method of claim 7, further comprising:

loading, using the computing system, the adaptive computing integrated circuit bit file into the adaptive computing integrated circuit.

9. The method of claim 8, wherein the loading occurs from a location remote to the adaptive computing integrated circuit.

10. The method of claim 8, wherein the loading occurs as a download from a network.

11. The method of claim 1, further comprising:

generating, using the computing system, a plurality of configuration information versions, each configuration information version corresponding to a configuration information version selection parameter of a plurality of configuration information version selection parameters.

12. The method of claim 11, wherein the plurality of configuration information version selection parameters comprises at least two of the following configuration information version selection parameters:

a competing operating mode, versatility for a plurality of operating modes, a selected operational feature set of a plurality of operational feature sets, selected operating conditions of a plurality of operation conditions, and a selected adaptive computing circuit version of a plurality of adaptive computing circuit versions.

13. The method of claim 1, further comprising:

compiling, using the computing system, the configuration information into a plurality of versions of adaptive computing integrated circuit bit files, each bit file version corresponding to a bit file version selection parameter of a plurality of bit file version selection parameters.

14. The method of claim 13, wherein the plurality of bit file version selection parameters comprises at least two of the following bit file version selection parameters:

a competing operating mode, versatility for a plurality of operating modes, a selected operational feature set of a plurality of operational feature sets, selected operating conditions of a plurality of operating conditions, and a selected adaptive computing circuit version of a plurality of adaptive computing circuit versions.

15. The method of claim 1, wherein step (c) further comprises:

scheduling, using the computing system, the algorithm over time according to a one to one (1;

1) correspondence between a plurality of algorithmic elements comprising the algorithm and the plurality of adaptive computing descriptive objects.

16. The method of claim 1, wherein step (c) further comprises:

generating, using the computing system, timing information within the configuration information, the timing information directing a configuration of the interconnection network to interconnect one or more heterogeneous computing elements of the adaptive computing integrated circuit prior to an arrival of corresponding operand data.

17. The method of claim 1, wherein each adaptive computing descriptive object of the plurality of adaptive computing descriptive objects comprises a description of a function in the scheduled algorithm to be performed by one or more of the heterogeneous computing elements, an input for the function, and an output for the function.

18. This method of claim 17, wherein each adaptive computing descriptive object of the plurality of adaptive computing descriptive objects further comprises a description of a memory resource for the function, an input for the memory resource, an output for the memory resource, and a connection between the function and the memory resource.

19. The method of claim 1, wherein, a selected adaptive computing descriptive object of the plurality of adaptive computing descriptive objects, describes a function of a plurality of functions, the plurality of functions comprising at least two of the following functions:

a plurality of linear operations, a plurality of non-linear operations, a plurality of finite state machine operations, a plurality of control sequences, a plurality of bit level manipulations, memory, and memory management.

20. A computing system for development of configuration information for an adaptive computing integrated circuit having a plurality of heterogeneous computing elements, each of the plurality of heterogeneous computing elements coupled to a reconfigurable interconnection network, the configuration information for configuring or reconfiguring the interconnection network to interconnect one or more of the plurality of the heterogeneous computing elements to perform at least a part of a selected algorithm, the system comprising:

a computer with one or more processors;

a scheduler implemented in the computer, and adapted to schedule the selected algorithm with a plurality of adaptive computing descriptive objects to produce a scheduled algorithm;

a memory coupled to the scheduler, the memory storing the plurality of adaptive computing descriptive objects; and

a compiler implemented in the computer, and coupled to the scheduler, the compiler generating the configuration information, from the scheduled algorithm and the plurality of adaptive computing descriptive objects, the configuration information used to configure or reconfigure the interconnection network to interconnect the one or more of the plurality of the heterogeneous computing elements for the performance of the at least part of the algorithm, each of the one or more of the plurality of the heterogeneous computing elements performing a corresponding computational task of the at least part of the algorithm.

21. The system of claim 20, further comprising:

a hardware description generator implemented in the computer, and coupled to the scheduler, the hardware description generator converting the adaptive computing circuit descriptive objects to a hardware description language file for fabrication of a fixed architecture computing integrated circuit.

22. The system of claim 20, wherein the scheduler selects the adaptable computing integrated circuit by:

generating, using the computer, a plurality of adaptive computing circuit versions from the plurality of adaptive computing descriptive objects;

scheduling, using the computer, the algorithm with the plurality of adaptive computing descriptive objects of each of the plurality of adaptive computing circuit versions; and

using a circuit version selection parameter of a plurality of circuit version selection parameters, selecting, using the computer, an adaptive computing circuit version from the plurality of adaptive computing circuit versions, to form the selected adaptive computing circuit version corresponding to the selected adaptive computing integrated circuit.

23. The system of claim 22, wherein the plurality of circuit version selection parameters comprises at least two of the following circuit version selection parameters power consumption, speed of operation, latency, bandwidth requirements, a competing operating mode, and versatility by a plurality of operating modes.

24. The system of claim 20, further comprising:

a profiler coupled to the scheduler, the profiler profiling, using the computer, the algorithm for performance on the adaptive computing integrated circuit.

25. The system of claim 24, wherein the profiling is based upon a plurality of data parameters, the plurality of data parameters comprising at least two of the following data parameters:

data location for static data;

data type;

input data size;

output data size;

data source location;

data destination location;

data pipeline length;

locality of reference;

distance of data movement;

speed of data movement;

data access frequency;

number of data load/stores, cache usage, register usage, memory usage, and data persistence.

26. The system of claim 24, wherein the profiler further profiling, using the computer, the algorithm for performance on the one or more processors.

27. The system of claim 20, wherein the compiler further compiling, using the computer, the configuration information into an adaptive computing integrated circuit bit file.

28. The system of claim 27, further comprising:

a configuration information provider, the configuration information provider loading, using the computer, the adaptive computing integrated circuit bit file into the adaptive computing integrated circuit.

29. The system of claim 28, wherein the loading occurs from a location remote to the adaptive computing integrated circuit.

30. The system of claim 28, wherein the loading occurs as a download from a network.

31. The system of claim 20, wherein the scheduler further generating, using the computer, a plurality of versions of configuration information, each configuration information version corresponding to a configuration information version selection parameter of a plurality of configuration information version selection parameters.

32. The system of claim 31, wherein the plurality of configuration information version selection parameters comprises at least two of the following configuration information version selection parameters:

a competing operating mode, versatility for a plurality of operating modes, a selected operational feature set of a plurality of operational feature sets, selected operating conditions of a plurality of operating conditions; and

a selected adaptive computing circuit version of a plurality of adaptive computing circuit versions.

33. The system of claim 20, wherein the compiler further compiling, using the computer, the configuration information into a plurality of versions of adaptive computing integrated circuit bit files, each bit file version corresponding to a bit file version selection parameter of a plurality of bit file version selection parameters.

34. The system of claim 33, wherein the plurality of bit file version selection parameters comprises at least two of the following bit file version selection parameters:

a competing operation mode, versatility for a plurality of operating modes, a selected operational feature set of a plurality of operational feature sets, selected operating conditions of a plurality of operating conditions, and a selected adaptive computing circuit version of a plurality of adaptive computing circuit versions.

35. The system of claim 20, wherein the scheduler further scheduling, using the computer, the algorithm over time according to a one to one (1:

1) correspondence between a plurality of algorithm elements comprising the algorithm and the plurality of adaptive computing descriptive objects.

36. The system of claim 20, wherein the scheduler further generating, using the computer, timing information within the configuration information, the timing information directing a configuration of interconnection network to interconnect at least one of the heterogeneous computing elements of the adaptive computing integrated circuit prior to an arrival of corresponding operand data.

37. The system of claim 20, wherein each adaptive computing descriptive object of the plurality of adaptive computing descriptive objects comprises a description of a function in the scheduled algorithm to be performed by one or more of the heterogeneous computing elements, an input for the function, and an output for the function.

38. The system of claim 37, wherein each adaptive computing descriptive object of the plurality of adaptive computing descriptive objects further comprises a description of a memory resource for the function, an input for the memory resource, an output for the memory resource, and a connection between the function and the memory resource.

39. The system of claim 20, wherein a selected adaptive computing descriptive object, of the plurality of adaptive computing descriptive objects, describes a function of a plurality of functions, the plurality of functions comprising at least two of the following functions a plurality of linear operations a plurality of non-linear operations, a plurality of finite state machine operations, a plurality of control sequences a plurality of bit level manipulations, memory, and memory management.

40. A storage medium storing machine executable software instructions which when executed on a computer develops configuration information for an adaptive computing integrated circuit having a plurality of heterogeneous computing elements, each of the plurality of heterogeneous computing elements adapted to being coupled to each other through a reconfigurable interconnection network, the configuration information for configuring or reconfiguring the interconnection network to interconnect one or more heterogeneous computing elements to perform at least a part of an algorithm, the medium storing instructions for:

selecting an algorithm for performance by the adaptive computing integrated circuit;

determining a plurality of adaptive computing descriptive objects for functions of the selected algorithm;

scheduling the selected algorithm with the plurality of adaptive computing descriptive objects to produce a scheduled algorithm; and

generating the configuration information, from the scheduled algorithm and the adaptive computing descriptive objects, for the performance of at least a part of the algorithm by the one or more of the plurality of heterogeneous computing elements.

41. The medium of claim 40, further comprising instructions for:

converting the adaptive computing descriptive objects to a hardware description language file for fabrication to form a fixed architecture computing integrated circuit.

42. The medium of claim 40, further comprising instructions for:

generating a plurality of adaptive computing circuit versions from the plurality of adaptive computing descriptive objects;

schedules the algorithm with the plurality of adaptive computing descriptive objects of each of the plurality of adaptive computing circuit versions; and

selects an adaptive computing circuit version from the plurality of adaptive computing circuit versions, using a circuit version selection parameter of a plurality of circuit version selection parameters, to form a selected adaptive computing circuit version corresponding with the adaptive computing integrated circuit.

43. The medium of claim 42, wherein the plurality of circuit version selection parameters comprises at least two of the following circuit version selection parameters power consumption, speed of operation, latency, bandwidth requirements, a competing operating mode, and versatility for a plurality of operating modes.

44. The medium of claim 40, further comprising instructions for:

profiling the algorithm for performance on the adaptive computing integrated circuit.

45. The medium of claim 44, wherein the profiling is based upon a plurality of data parameters, the plurality of data parameters comprising at least two of the following data parameters:

data location for static data;

data type;

input data size;

output data size;

data source location;

data destination location, data pipeline length, locality of reference, distance of data movement, speed of data movement, data access frequency, number of data load/stores, cache usage;

register usage;

memory usage, and data persistence.

46. The medium of claim 40, further comprising instructions for:

profiling the algorithm for performance on one or more processors of the computer.

47. The medium of claim 40, further comprising instructions for:

compiling the configuration information into an adaptive computing integrated circuit bit file.

48. The medium of claim 47, further comprising instructions for:

loading the adaptive computing integrated circuit bit file into the adaptive computing integrated circuit.

49. The medium of claim 48, wherein the loading provides for loading occurring from a location remote to the adaptive computing integrated circuit.

50. The medium of claim 48, wherein the loading provides for loading occurring as a download from a network.

51. The medium of claim 40, further comprising instructions for:

generating a plurality of versions of configuration information, each configuration information version corresponding to a configuration information version selection parameter of a plurality of configuration information version selection parameters.

52. The medium of claim 51, wherein the plurality of configuration information version selection parameters comprises at least two of the following configuration information version selection parameters:

a competing operating mode, versatility for a plurality of operating modes, a selected operational feature set of a plurality of operational feature sets, selected operating conditions of a plurality of operating conditions, and a selected adaptive computing circuit version of a plurality of adaptive computing circuit versions.

53. The medium of claim 40, further comprising instructions for:

compiling the configuration information into a plurality of versions of adaptive computing integrated circuit bit files, each bit file version corresponding to a bit file version selection parameter of a plurality of bit file version selection parameters.

54. The medium of claim 53, wherein the plurality of bit file version selection parameters comprises at least two of the following bit file version selection parameters:

a competing operating mode, versatility for a plurality of operating modes, a selected operational feature set of a plurality of operational feature sets, selected operating conditions of plurality of operating conditions, and a selected adaptive computing circuit version of a plurality of adaptive computing circuit versions.

55. The medium of claim 40, further comprising instructions for:

scheduling the algorithm over time according to a one to one (1;

1) correspondence between a plurality of algorithmic elements comprising the algorithm and the plurality of adaptive computing descriptive objects.

56. The medium of claim 40, further comprising instructions for:

generating timing information within the configuration information, the timing information directing a configuration of the adaptive computing integrated circuit prior to an arrival of corresponding operand data.

57. The medium of claim 40, wherein each adaptive computing descriptive object of the plurality of adaptive computing descriptive objects comprises a description of a function, an input for the function, and an output for the function.

58. The medium of claim 57, wherein each adaptive computing descriptive object of the plurality of adaptive computing descriptive objects further comprises a description of a memory resource for the function, an input for the memory resource, an output for the memory resource and a connection between the function and the memory resource.

59. The medium of claim 40, wherein a selected adaptive computing descriptive object, of the plurality of adaptive computing descriptive objects, describes a function of a plurality of functions, the plurality of functions comprising at least two of the following functions:

a plurality of linear operations, a plurality of non-linear operations, a plurality of finite state machine operations, a plurality of control sequences, a plurality of bit level manipulations, memory, and memory management.

60. A computer implemented method for development of corresponding configuration information for an adaptive computing integrated circuit having a plurality of heterogeneous computing elements, each of which is adapted to being coupled to each other through a reconfigurable interconnection network, the configuration information configuring or reconfiguring the interconnection network to interconnect one or more of the plurality of the heterogeneous computing elements to perform at least a part of an algorithm, the method comprising

selecting the algorithm for performance by the adaptive computing integrated circuit;

profiling, using a computing system, the algorithm for performance on the adaptive computing integrated circuit;

determining, using the computing system, a plurality of adaptive computing descriptive objects, each adaptive computing descriptive object of the plurality of adaptive computing descriptive objects including a description of a function to be performed by one or more of the heterogeneous computing elements, an input for the function, and an output for the function;

scheduling, using the computing system, the algorithm with the plurality of adaptive computing descriptive objects; and

from the selected scheduled algorithm generating, using the computing system, the configuration information and compiling the configuration information into an adaptive computing integrated circuit bit file for the performance of a corresponding computational task of the algorithm by one or more of the heterogeneous computing elements of the adaptive computing integrated circuit.

61. A computer implemented method for developing an adaptive computing integrated circuit to perform at least part of an algorithm, the adaptive computing integrated circuit including a plurality of heterogeneous computing elements being coupled to each other by a reconfigurable interconnection network, the method comprising:

determining, using a computing system, a plurality of adaptive computing descriptive objects associated with functions of the algorithm;

determining, using the computing system, a plurality of adaptive computing integrated circuit versions having a description of heterogeneous computing elements, each performing a function corresponding with at least one of the plurality of adaptive computing descriptive objects;

scheduling, using the computing system, the algorithm with the plurality of adaptive computing descriptive objects to produce a scheduled algorithm;

selecting, using the computing system, an adaptive computing integrated circuit version from the plurality of adaptive computing integrated circuit versions using a circuit version selection parameter of a plurality of circuit version selection parameters; and

converting, using the computing system, the selected adaptive computing integrated circuit version to the adaptive computing integrated circuit.

62. The method of claim 61, further comprising converting, using the computing system, the selected adaptive computing circuit version to a hardware description language file for use in the fabrication of the adaptive computing integrated circuit.

63. The method of claim 61, wherein the plurality of circuit version selection parameters comprises at least two of the following circuit version selection parameters:

power consumption, speed of operation, latency, bandwidth requirements, a competing operating mode, and versatility for a plurality of operating modes.

64. The method of claim 61, wherein step (a) further comprises:

profiling, using the computing system, the algorithm for performance on the one or more heterogeneous computing elements of the adaptive computing integrated circuit.

65. The method of claim 64, wherein the profiling is based upon a plurality of data parameters, the plurality of data parameters comprising at least two of the following parameters:

data location for static data;

data type, input data size;

output data size;

data source location;

data destination location;

data pipeline length;

locality of reference;

distance of data movement;

speed of data movement;

data access frequency;

number of data load/stores;

cache usage;

register usage;

memory usage, and data persistence.

66. The method of claim 61, further comprising determining, using the computing system, configuration information to configure the interconnection network of the adaptive computing integrated circuit to interconnect the heterogeneous computing elements to perform a function of the algorithm;

and compiling the configuration information into an adaptive computing integrated circuit bit file.

67. The method of claim 66, further comprising generating, using the computing system, a plurality of configuration information versions, each configuration information version corresponding to a configuration information version selection parameter of a plurality of configuration information version selection parameters.

68. The method of claim 67, wherein the plurality of configuration information version selection parameters comprises at least two of the following configuration information version selection parameters:

a competing operating mode, versatility for a plurality of operating modes, a selected operational feature set of a plurality of operational feature sets, selected operating conditions of a plurality of operation conditions, and a selected adaptive computing circuit version of a plurality of adaptive computing circuit versions.

69. The method of claim 61, wherein each adaptive computing descriptive object of the plurality of adaptive computing descriptive objects comprises a description of a function to be performed by one or more of the heterogeneous computing elements, an input for the function, and an output for the function.

70. The method of claim 69, wherein each adaptive computing descriptive object of the plurality of adaptive computing descriptive objects further comprises a description of a memory resource for the function, an input for the memory resource, an output for the memory resource, and a connection bet,ween the function and the memory resource.

71. The method of claim 61, wherein, a selected adaptive computing descriptive object of the plurality of adaptive computing descriptive objects, describes a function of a plurality of functions, the plurality of functions comprising at least two of the following functions:

a plurality of linear operations, a plurality of non-linear operations, a plurality of finite state machine operations, a plurality of control sequences, a plurality of bit level manipulations, memory, and memory management.