Continuous application and decompression of test patterns to a circuit-under-test
First Claim
1. An apparatus to test an integrated circuit, comprising:
- a linear feedback shift register (LFSR) within the integrated circuit;
automatic testing equipment located external to the integrated circuit; and
a plurality of registers within the integrated circuit and coupled between outputs of the automatic testing equipment and inputs of the LFSR.
2 Assignments
0 Petitions
Accused Products
Abstract
A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear feedbackstate machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The circuit further includes scan chains for testing circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern.
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Citations
16 Claims
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1. An apparatus to test an integrated circuit, comprising:
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a linear feedback shift register (LFSR) within the integrated circuit; automatic testing equipment located external to the integrated circuit; and a plurality of registers within the integrated circuit and coupled between outputs of the automatic testing equipment and inputs of the LFSR. - View Dependent Claims (2, 3, 4, 5)
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6. An apparatus to test an integrated circuit, comprising:
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a plurality of registers within the integrated circuit; a phase shifter within the integrated circuit; and a linear feedback shift register (LFSR) having a plurality of inputs coupled to respective outputs of the plurality of registers and having a plurality of outputs coupled to respective inputs of the phase shifter. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A method of testing an integrated circuit, comprising:
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loading a register within the integrated circuit with a compressed test pattern; transferring the compressed test pattern from an output of the register to an input of a linear feedback shift register (LFSR); and decompressing the compressed test pattern, wherein the transferring and the decompressing of the compressed test pattern occur simultaneously. - View Dependent Claims (13, 14, 15, 16)
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Specification