Context-corrupting context switching

• US 7,478,394 B1
• Filed: 06/04/2001
• Issued: 01/13/2009
• Est. Priority Date: 06/04/2001
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Chevrot, Jean-Marc, de Dinechin, Christophe
• Primary Examiner(s): An; Meng-Ai
• Assistant Examiner(s): To; Jennifer N
• Application Number:
  US09/873,875
• Time in Patent Office: 2,780 Days
• Field of Search: 718/1, 718/100, 718/102, 718/103, 718/107, 718/108, 712/42, 712/240, 712/28.228, 712/228, 710/264, 710/261, 726/21
• US Class Current: 718/108
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: G06F 9/4555 Para-virtualisation, i.e. guest operating system has to be modified
• CPC Class Codes: G06F 9/462 with multiple register sets
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

A virtual machine application interrupts execution of a host OS under software control at a predetermined interruption point, instead of interrupting the execution at an arbitrary instruction. The context of the host OS is saved by using an inconsequential register as temporary storage. Context of the host OS is restored by using an inconsequential register as temporary storage.

Claims

1. A method of switching context on a processor, the method comprising:

saving the context under software control using an inconsequential register;

preventing the processor from changing the context while the context is being saved; and

thereafter restoring the context using an inconsequential register.

2. The method of claim 1, wherein the inconsequential register is used as a temporary storage in lieu of a privileged register.

3. The method of claim 1, wherein the context is saved at a predetermined interruption point.

4. The method of claim 1, wherein the context is switched between a host operating system and a virtual machine application, the virtual machine application controlling the context switch.

5. The method of claim 4, wherein the inconsequential register is used to pass information to the virtual machine application.

6. The method of claim 1, wherein the context is switched using an IA-64 processor.

7. The method of claim 6, wherein the inconsequential register is a caller-save register.

8. The method of claim 6, wherein the inconsequential register is a branch register.

9. The method of claim 1, wherein the context is restored by using a branch register to perform an indirect branch.

10. The method of claim 1, wherein content of the inconsequential register is corrupted during the context switch.

11. The method of claim 1, wherein using the inconsequential register includes storing an address in the inconsequential register, the address indicating a memory location at which the context will be saved.

12. The method of claim 1, wherein the inconsequential register does not store context at a predetermined interruption point.

13. The method of claim 1, wherein the context is stored in memory other than the inconsequential register.

14. A method of switching context between a host OS and a virtual machine on a processor, the processor having privileged registers, the processor having access to other memory, the method comprising:

giving the virtual machine access to the privileged registers;

using at least one privileged register as temporary storage to save the context in the other memory at a predetermined interruption point;

preventing the processor from changing the context while the context is being saved; and

restoring the context using an inconsequential register;

the virtual machine application controlling the context switch.

15. Apparatus comprising:

a processor including a plurality of registers; and

a virtual machine application for commanding the processor to switch context by saving the context under software control using an inconsequential register of the processor as temporary storage; and

preventing the processor from changing the context while the context is being saved; and

to restore context by using the inconsequential register.

16. The apparatus of claim 15, wherein the inconsequential register is used as a temporary storage in lieu of a privileged register.

17. The apparatus of claim 15, wherein the context is saved at a predetermined interruption point.

18. The apparatus of claim 15, further comprising a host OS;

wherein the context is switched between the host OS and the virtual machine application; and

wherein the virtual machine application controls the context switch.

19. The apparatus of claim 18, wherein the inconsequential register is used to pass information to the virtual machine application.

20. The apparatus of claim 15, wherein the processor is an IA-64 processor.

21. The apparatus of claim 20, wherein the inconsequential register is a caller-save register.

22. The apparatus of claim 20, wherein the inconsequential register is a branch register.

23. The apparatus of claim 15, wherein the virtual machine application commands the processor to restore the context using the inconsequential register as temporary storage.

24. The apparatus of claim 23, wherein the context is restored by using a branch register to perform an indirect branch.

25. An article comprising computer memory encoded with instructions for commanding a processor to switch context by saving the context under software control using an inconsequential register of the processor as temporary storage;

and preventing the processor from changing the context while the context is being saved;

the instructions further commanding the processor to restore context using the inconsequential register.