Memory arrays using nanotube articles with reprogrammable resistance

• US 7,479,654 B2
• Filed: 11/15/2005
• Issued: 01/20/2009
• Est. Priority Date: 05/09/2005
• Status: Active Grant

• Current Assignee: Nantero Incorporated
• Original Assignee: Nantero Incorporated
• Inventors: Bertin, Claude L., Sivarajan, Ramesh, Rueckes, Thomas, Guo, Frank, Strasburg, Max, Huang, X. M. Henry, Meinhold, Mitchell, Konsek, Steven L.
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): Chiu; Tsz K
• Application Number:
  US11/274,967
• Publication Number:
  US 20060250856A1
• Time in Patent Office: 1,162 Days
• Field of Search: 257/14, 257/24, 257/296, 257/290, 257/130, 257/E51.04, 257/40, 365/163, 365/129, 365/177
• US Class Current: 257/40
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 2213/16 Memory cell being a nanotube, e.g. suspended nanotube
• CPC Class Codes: G11C 2213/19 Memory cell comprising at least a nanowire and only two terminals
• CPC Class Codes: G11C 2213/35 Material including carbon, e.g. graphite, grapheme
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.

Claims

1. A memory array, comprising:

a plurality of memory cells, each memory cell receiving a bit line, a first word line, and a second word line, each memory cell including;

a cell selection circuit operably coupled to the first word line and the bit line to select the memory cell in response to activation of at least one of the bit line and the first word line; and

a two-terminal switching device having only first and second conductive terminals to access and program the switching device wherein each of the first and second conductive terminals is coupled to a nanotube article, the first terminal operably coupled to the cell selection circuit and the second terminal operably coupled to the second word line; and

a memory operation circuit operably coupled to the bit line, the first word line, and the second word line of each cell,

said operation circuit including circuitry to activate at least one of the bit line and the first word line to select the memory cell for access or programming and including programming circuitry to apply an electrical stimulus to program a memory state in said nanotube article, said programming circuit to apply a first electrical stimulus to at least one of the bit line, first word line, and second word line, in which said first electrical stimulus changes the resistance of the nanotube article between the first and second terminals to a relatively high resistance and said programming circuit to apply a second electrical stimulus to at least one of the bit line, first word line, and second word line, in which said the second electrical stimulus changes the resistance of the nanotube article between the first and second terminals to a relatively low resistance,

wherein a relatively high resistance of the nanotube article corresponds to a first informational state of the memory cell, and wherein a relatively low resistance of the nanotube article corresponds to a second informational state of the memory cell.

2. The array of claim 1, wherein the first and second informational states are nonvolatile.

3. The array of claim 1, wherein the resistance of the first state is at least about ten times larger than the resistance of the second state.

4. The array of claim 1, wherein the cell selection circuit includes a transistor with a gate, a source, and a drain.

5. The array of claim 4, wherein the gate is in electrical contact with the first word line, the source is in electrical contact with the first conductive terminal, and the drain is in electrical contact with the bit line.

6. The array of claim 1, wherein the cell selection circuit includes a FET.

7. The array of claim 1, wherein said operation circuit reads an informational state of the memory cell by selecting the cell by activating one of the bit line and the first word line and applying a read stimulus to the bit line.

8. The array of claim 7, wherein the read stimulus comprises applying a floating voltage, and the operation circuit reads the informational state of the cell by determining whether the voltage on the bit line decays below a threshold value.

9. The array of claim 7, wherein reading the informational state of the memory cell is a non-destructive read-out operation.

10. The array of claim 1, wherein said operation circuit includes a latch corresponding to each memory cell and records the informational state of the memory cell in the corresponding latch before erasing the memory cell.

11. The array of claim 1, wherein the operation circuit includes circuitry to produce an erase operation for the first electrical stimulus.

12. The array of claim 11, wherein the erase operation comprises applying one or more voltage pulses, wherein an amplitude of the pulses, a waveform of the pulses, and a number of the pulses together are sufficient to change the device to the first state.

13. The array of claim 1, wherein the operation circuit includes circuitry to produce a program operation for the second electrical stimulus.

14. The array of claim 13, wherein the program operation comprises applying one or more voltage pulses, wherein an amplitude of the pulses, a waveform of the pulses, and a number of the pulses together are sufficient to change the device to the second state.

15. The array of claim 1, wherein the nanotube article comprises a region of nanotube fabric of defined orientation.

16. The array of claim 1, wherein the first and second terminals are metal.

17. The array of claim 1, wherein the metal comprises at least one Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, TiAu, TiCu, TiPd, PbIn, and TiW.

18. The array of claim 1, wherein the operation circuit applies a select voltage to the first word line to select the cell and an erase voltage to the second word line to change the resistance of the nanotube article to a relatively high resistance.

19. The array of claim 1, wherein the operation circuit applies a select voltage to the first word line to select the cell and a program voltage to the second word line to change the resistance of the nanotube article to a relatively low resistance.

20. The array of claim 1, wherein the operation circuit applies a select voltage to the first word line to select the cell and a program voltage to the bit line to change the resistance of the nanotube article to a relatively low resistance.

21. The array of claim 1, wherein the operation circuit applies a select voltage to the first word line to select the cell and an erase voltage to the bit line to change the resistance of the nanotube article to a relatively high resistance value.

22. A memory cell, comprising:

a cell selection circuit in electrical communication with a bit line and a first word line to select the memory cell in response to activation of at least one of the bit line and the first word line; and

a two-terminal nanotube switching device having only first and second conductive terminals to access and program the switching device wherein each of the first and second conductive terminals is coupled to a nanotube article, the first terminal in electrical communication with the cell selection circuit and the second terminal in electrical communication with a second word line,

wherein selecting the memory cell and applying a first electrical stimulus to at least one of the bit line, first word line, and second word line changes a resistance of the switching device between the first and second terminals from a relatively low resistance to a relatively high resistance, and

wherein selecting the memory cell and applying a second electrical stimulus to at least one of the bit line, first word line, and second word line changes a resistance of the switching device between the first and second terminals from a relatively high resistance to a relatively low resistance,

wherein the relatively high resistance between the first and second terminals corresponds to a first informational state of the memory cell, and wherein the relatively low resistance between the first and second terminals corresponds to a second informational state of the memory cell.

23. The cell of claim 22, wherein the first and second informational states are non-volatile.

24. The cell of claim 22, wherein the resistance of the first informational state is at least about ten times larger than the resistance of the second state.

25. The cell of claim 22, wherein the cell selection circuit includes a transistor with a gate, a source, and a drain.

26. The cell of claim 25, wherein the gate is in electrical communication with the first word line, the source is in electrical communication with the first conductive terminal, and the drain is in electrical communication with the bit line.

27. The cell of claim 22, wherein the cell selection circuit comprises a FET.

28. The cell of claim 22, wherein the first electrical stimulus comprises applying one or more voltage pulses, wherein an amplitude of the pulses, a waveform of the pulses, and a number of the pulses together are sufficient to change the device to the first informational state.

29. The cell of claim 22, wherein the second electrical stimulus comprises applying one or more voltage pulses, wherein an amplitude of the pulses, a waveform of the pulses, and a number of the pulses together are sufficient to change the device to the second informational state.

30. The cell of claim 22, wherein the nanotube article comprises a region of nanotube fabric of defined orientation.

31. The cell of claim 22, wherein the first and second terminals are metal.

32. The cell of claim 22, wherein the metal comprises at least one of Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, TiAu, TiCu, TiPd, PbIn, and TiW.