Memory arrays using nanotube articles with reprogrammable resistance
First Claim
1. A memory array, comprising:
- a plurality of memory cells, each memory cell receiving a bit line, a first word line, and a second word line, each memory cell including;
a cell selection circuit operably coupled to the first word line and the bit line to select the memory cell in response to activation of at least one of the bit line and the first word line; and
a two-terminal switching device having only first and second conductive terminals to access and program the switching device wherein each of the first and second conductive terminals is coupled to a nanotube article, the first terminal operably coupled to the cell selection circuit and the second terminal operably coupled to the second word line; and
a memory operation circuit operably coupled to the bit line, the first word line, and the second word line of each cell,said operation circuit including circuitry to activate at least one of the bit line and the first word line to select the memory cell for access or programming and including programming circuitry to apply an electrical stimulus to program a memory state in said nanotube article, said programming circuit to apply a first electrical stimulus to at least one of the bit line, first word line, and second word line, in which said first electrical stimulus changes the resistance of the nanotube article between the first and second terminals to a relatively high resistance and said programming circuit to apply a second electrical stimulus to at least one of the bit line, first word line, and second word line, in which said the second electrical stimulus changes the resistance of the nanotube article between the first and second terminals to a relatively low resistance,wherein a relatively high resistance of the nanotube article corresponds to a first informational state of the memory cell, and wherein a relatively low resistance of the nanotube article corresponds to a second informational state of the memory cell.
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Accused Products
Abstract
A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.
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Citations
32 Claims
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1. A memory array, comprising:
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a plurality of memory cells, each memory cell receiving a bit line, a first word line, and a second word line, each memory cell including; a cell selection circuit operably coupled to the first word line and the bit line to select the memory cell in response to activation of at least one of the bit line and the first word line; and a two-terminal switching device having only first and second conductive terminals to access and program the switching device wherein each of the first and second conductive terminals is coupled to a nanotube article, the first terminal operably coupled to the cell selection circuit and the second terminal operably coupled to the second word line; and a memory operation circuit operably coupled to the bit line, the first word line, and the second word line of each cell, said operation circuit including circuitry to activate at least one of the bit line and the first word line to select the memory cell for access or programming and including programming circuitry to apply an electrical stimulus to program a memory state in said nanotube article, said programming circuit to apply a first electrical stimulus to at least one of the bit line, first word line, and second word line, in which said first electrical stimulus changes the resistance of the nanotube article between the first and second terminals to a relatively high resistance and said programming circuit to apply a second electrical stimulus to at least one of the bit line, first word line, and second word line, in which said the second electrical stimulus changes the resistance of the nanotube article between the first and second terminals to a relatively low resistance, wherein a relatively high resistance of the nanotube article corresponds to a first informational state of the memory cell, and wherein a relatively low resistance of the nanotube article corresponds to a second informational state of the memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A memory cell, comprising:
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a cell selection circuit in electrical communication with a bit line and a first word line to select the memory cell in response to activation of at least one of the bit line and the first word line; and a two-terminal nanotube switching device having only first and second conductive terminals to access and program the switching device wherein each of the first and second conductive terminals is coupled to a nanotube article, the first terminal in electrical communication with the cell selection circuit and the second terminal in electrical communication with a second word line, wherein selecting the memory cell and applying a first electrical stimulus to at least one of the bit line, first word line, and second word line changes a resistance of the switching device between the first and second terminals from a relatively low resistance to a relatively high resistance, and wherein selecting the memory cell and applying a second electrical stimulus to at least one of the bit line, first word line, and second word line changes a resistance of the switching device between the first and second terminals from a relatively high resistance to a relatively low resistance, wherein the relatively high resistance between the first and second terminals corresponds to a first informational state of the memory cell, and wherein the relatively low resistance between the first and second terminals corresponds to a second informational state of the memory cell. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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Specification