Selectively disabled output

• US 7,479,798 B1
• Filed: 05/16/2006
• Issued: 01/20/2009
• Est. Priority Date: 05/16/2006
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Reese, Laura
• Primary Examiner(s): Barnie; Rexford
• Assistant Examiner(s): Tran; Thienvu V
• Application Number:
  US11/435,416
• Time in Patent Office: 980 Days
• Field of Search: 326/8, 326/10, 326/16, 713/193, 713/194
• US Class Current: 326/8
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17768 for security

Abstract

Circuits, methods, and apparatus are directed to an integrated circuit having a disabling element that can disable a reading of data from the circuit. Once the disabling element is set to not allow a reading of the data, the disabling element cannot be changed to allow a reading of the data. The data may be configuration data or internal data stored within the integrated circuit. Examples of the disabling element include a memory element, a break in a circuit line, and an input pad configuration.

Claims

1. An integrated circuit comprising:

a plurality of storage circuits capable of storing data;

a readout circuit for outputting the data; and

a disabling element, wherein a first state of the disabling element allows a reading of the data and wherein a second state disables the reading of the data,

wherein once the disabling element is in the second state, the disabling element cannot enter the first state, and

wherein when the disabling element is in the second state, the outputting of the data is prevented, and wherein the disabling element includes a non-repairable break in a circuit line, the circuit line being used for sending data from the storage circuits to a data output of the integrated circuit.

2. The integrated circuit of claim 1, wherein the disabling element comprises a fuse.

3. The integrated circuit of claim 1, wherein the disabling element comprises an input pad.

4. The integrated circuit of claim 1, wherein the disabling element comprises a memory element, wherein the memory element is a one-time programmable memory.

5. The integrated circuit of claim 1, wherein the integrated circuit is a field programmable gate array.

6. The integrated circuit of claim 1, wherein the storage circuits capable of storing data comprise RAM.

7. The integrated circuit of claim 1, wherein the storage circuits capable of storing data comprise registers.

8. The integrated circuit of claim 1, wherein the disabling element comprises an anti-fuse.

9. An integrated circuit comprising:

a plurality of storage circuits capable of storing data and that receives at least one read enable signal when the data is read out;

a readout circuit for outputting the data; and

a disabling element, wherein a first state of the disabling element allows a reading of the data and wherein a second state disables the reading of the data;

wherein once the disabling element is in the second state, the disabling element cannot enter the first state; and

wherein when the disabling element is in the second state, the outputting of the data from the storage circuits is prevented, and wherein the disabling element inhibits the read enable signal from being received by the storage circuits.

10. The integrated circuit of claim 9, wherein the disabling element comprises a fuse.

11. The integrated circuit of claim 9, wherein the disabling element comprises a memory element.

12. The integrated circuit of claim 11, wherein the memory element is a one-time programmable memory.

13. The integrated circuit of claim 9, wherein the integrated circuit is a field programmable gate array.

14. The integrated circuit of claim 9, wherein the storage circuits capable of storing data comprise RAM.

15. The integrated circuit of claim 9, wherein the storage circuits capable of storing data comprise registers.

16. The integrated circuit of claim 9, wherein the disabling element comprises an anti-fuse.