Programmable differential signaling system

• US 7,479,805 B1
• Filed: 08/01/2007
• Issued: 01/20/2009
• Est. Priority Date: 02/25/2005
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Cline, Ronald L., Zhou, Shi-dong, Nguyen, Andy T., Huang, Gubo
• Primary Examiner(s): Le; Don P
• Application Number:
  US11/888,790
• Time in Patent Office: 538 Days
• Field of Search: 326/26, 326/27, 326 82- 87
• US Class Current: 326/83
• CPC Class Codes: H04L 25/0264 Arrangements for coupling to transmission lines duplexing arrangements H04L5/14; line equalisers, line build-out devices H04L25/03878
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0288 the shape being matched to the transmission line pre-equalisation per se H04L25/03343

Abstract

A programmable differential signaling system includes a programmable bias generator and a plurality of input/output modules. The programmable bias generator is operably coupled to generate a first global bias signal and a second global signal based on desired signal properties of one of a plurality of differential signaling conventions. The a plurality of input/output modules is operably coupled to convert between differential signaling and single ended signaling, wherein actual signal properties of the differential signaling are regulated based on the first and second global bias signals to substantially equal the desired signal properties.

Claims

1. A low voltage differential signal (LVDS) driver comprises:

a first LVDS node;

a second LVDS node;

a load impedance circuit operably coupled between the first and second LVDS nodes; and

a switching circuit operably coupled to provide a differential signal at the first and second LVDS nodes in accordance with an input signal, wherein the switching circuit includes a plurality of current controlled switching transistor circuits, each current controlled switching transistor circuit comprising;

a cascode transistor having an input operably coupled to receive a bias control signal; and

a switching transistor coupled in series with the cascode transistor, wherein an input of the switching transistor is operably coupled to receive a switching signal in accordance with the input signal;

a first operational amplifier having a first input, a second input, and an output, wherein the first input of the first operational amplifier is operably coupled to receive a first global biasing signal, the second input of the first operational amplifier is operably coupled to receive a coupling node of the cascode transistor to the switching transistor, and the output of the first operational amplifier provides the bias control signal to a first pairing of the cascode transistor and the switching transistor; and

a second operational amplifier having a first input, a second input, and an output, wherein the first input of the second operational amplifier is operably coupled to receive a second global biasing signal, the second input of the second operational amplifier is operably coupled to receive a coupling node of the cascode transistor to the switching transistor, and the output of the second operational amplifier provides the bias control signal to a second pairing of the cascode transistor and the switching transistor.

2. The LVDS driver of claim 1, wherein the load impedance circuit comprises:

a first gated impedance network operably coupled to the first and second LVDS nodes; and

a second gated impedance network operably coupled in parallel with the first gated impedance, wherein, when active, a parallel combination of the first and second gated impedance networks establishes impedance of the LVDS impedance circuit.

3. The LVDS driver of claim 2, wherein the load impedance circuit comprises:

the first gated impedance network including a first transistor coupled in series with first a resistor, wherein an input of the first transistor is operably coupled to receive an enable signal; and

the second gated impedance network including a second transistor coupled in series with a second resistor, wherein an input of the second transistor is operably coupled to receive the enable signal.

4. The LVDS driver of claim 1 further comprises:

a first multiplexer operably coupled to provide the output of the first operational amplifier as the bias control signal to the first pairing of the cascode transistor and the switching transistor when a differential enable signal is active and to provide power supply rail voltage as the bias control signal to the first pairing of the cascode transistor and the switching transistor when the differential enable signal is inactive; and

a second multiplexer operably coupled to provide the output of the second operational amplifier as the bias control signal to the second pairing of the cascode transistor and the switching transistor when the differential enable signal is active and to provide a ground rail voltage as the bias control signal to the second pairing of the cascode transistor and the switching transistor when the differential enable signal is inactive.