PLL with dual edge sensitivity

• US 7,479,815 B1
• Filed: 03/01/2006
• Issued: 01/20/2009
• Est. Priority Date: 03/01/2005
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Sequoia Communications Corporation
• Inventors: Groe, John B., Viani, Paul Lawrence
• Primary Examiner(s): Wells, Kenneth B
• Assistant Examiner(s): Jager, Ryan C
• Application Number:
  US11/367,023
• Time in Patent Office: 1,056 Days
• Field of Search: 327/115, 327/117, 327/147, 327/148, 327/156, 327/157, 327/160, 331/34, 331/DIG.2, 331/25, 331/17, 377 47- 48, 377/52, 375373-376
• US Class Current: 327/156
• CPC Class Codes: H03K 23/667 by switching the base during a counting cycle
• CPC Class Codes: H03L 7/193 the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider

Abstract

A divider apparatus for use within a phase-locked loop having an output terminal at which an output frequency is produced. The apparatus includes a prescalar circuit configured to produce a prescaled signal by dividing the output frequency in response to a mode select signal. A first programmable counter is disposed to receive the prescaled signal and to produce the mode select signal. In addition, a second programmable counter is disposed to receive the prescaled signal and to produce a divided signal utilized by the phase-locked loop. The apparatus further includes a control circuit connected to the first programmable counter and to the second programmable counter, the control circuit providing a first resynchronization signal to the first programmable counter and a second resynchronization signal to the second programmable counter.

Claims

1. A divider apparatus for use within a phase-locked loop having an output terminal at which an output frequency is produced, the apparatus comprising:

a prescalar circuit configured to produce a prescaled signal by dividing the output frequency in accordance with a defined divider value, the prescalar circuit including at least a resynchronization element and a prescalar front-end configured to generate an intermediate signal characterized by a 50% duty cycle;

a first programmable counter disposed to receive the prescaled signal, said first programmable counter characterized by a first effective program counter value of A/2, wherein A comprises an integral value;

a second programmable counter disposed to receive the prescaled signal and to produce a divided signal utilized within the phase-locked loop, said second programmable counter characterized by a second effective program counter value of B/2, wherein B comprises an integral value; and

a control circuit connected to the first programmable counter and to the second programmable counter wherein the control circuit generates, when A comprises an odd value and B comprises an even value, a first resynchronization signal causing resynchronization of the first programmable counter with respect to a trailing edge of the waveform defining the prescaled signal and a second resynchronization signal causing resynchronization of the second programmable counter with respect to a leading edge of the waveform.

2. A divider apparatus for use within a phase-locked loop having an output terminal at which an output frequency is produced, the apparatus comprising:

a prescalar circuit configured to produce a prescaled signal by dividing the output frequency in accordance with a defined divider value, the prescalar circuit including at least a resynchronization element and a prescalar front-end configured to generate an intermediate signal characterized by a 50% duty cycle;

a first programmable counter disposed to receive the prescaled signal, said first programmable counter characterized by a first effective program counter value of A/2, wherein A comprises an integral value;

a second programmable counter disposed to receive the prescaled signal and to produce a divided signal utilized within the phase-locked loop, said second programmable counter characterized by a second effective program counter value of B/2, wherein B comprises an integral value; and

a control circuit connected to the first programmable counter and to the second programmable counter, the control circuit providing a sequence of first resynchronization signals to the first programmable counter and a sequence of second resynchronization signals to the second programmable counter wherein successive ones of the first resynchronization signals result in the first programmable counter being resynchronized alternately with respect to leading and trailing edges of a waveform defining the prescaled signal when A is comprised of an even value and B is comprised of an odd value.

3. The apparatus of claim 2 wherein successive ones of the second resynchronization signals result in the second programmable counter being resynchronized alternately with respect to trailing and leading edges of the waveform.

4. In a phase-locked loop having an output terminal at which an output frequency is produced, a signal frequency division method comprising:

dividing the output frequency in accordance with a defined divider value so as to produce a prescaled signal, wherein the dividing includes generating, in accordance with a mode select signal, an intermediate signal characterized by a 50% duty cycle,

generating the mode select signal based upon the prescaled signal, wherein the generating the mode select signal is effected using a first programmable counter characterized by a first effective program counter value of A/2 wherein A comprises an integral value;

performing counting operations using the prescaled signal so as to produce a divided signal utilized within the phase-locked loop, wherein the performing counting operations using the prescaled signal is effected using a second programmable counter characterized by a second effective program counter value of B/2 wherein B comprises an integral value; and

resynchronizing, when A comprises an odd value and B comprises an even value, the first programmable counter with respect to a trailing edge of the waveform defining the prescaled signal and the second programmable counter with respect to a leading edge of the waveform.

5. In a phase-locked loop having an output terminal at which an output frequency is produced, a signal frequency division method comprising:

dividing the output frequency in accordance with a defined divider value so as to produce a prescaled signal, wherein the dividing includes generating, in accordance with a mode select signal, an intermediate signal characterized by a 50% duty cycle;

generating the mode select signal based upon the prescaled signal, wherein the generating the mode select signal is effected using a first programmable counter characterized by a first effective program counter value of A/2 wherein A comprises an integral value;

performing counting operations using the prescaled signal so as to produce a divided signal utilized within the phase-locked loop, wherein the performing counting operations using the prescaled signal is effected using a second programmable counter characterized by a second effective program counter value of B/2 wherein B comprises an integral value; and

alternately resynchronizing, when A is comprised of an even value and B is comprised of an odd value, the first programmable counter with respect to leading and trailing edges of a waveform defining the prescaled signal and the second programmable counter with respect to trailing and leading edges of the waveform.

6. A phase-locked loop module, comprising:

a voltage-controlled oscillator for generating an output signal of a frequency determined by a control voltage;

a divider circuit for dividing the output signal to produce a frequency-divided signal, the divider including a prescalar circuit configured to produce a prescaled signal by dividing the frequency of the output signal, a first programmable counter and a second programmable counter connected to the output of the prescalar circuit, and a control circuit operatively coupled to the first programmable counter and the second programmable counter, wherein the first programmable counter is characterized by a first effective program counter value of A/2 and the second programmable counter is characterized by a second effective program counter value of B/2 wherein each of A and B may comprise an odd or even integral value, and wherein the control circuit is configured to provide a first resynchronization signal to the first programmable counter and a second resynchronization signal to the second programmable counter, and wherein, when A comprises an odd value and B comprises an even value, the first resynchronization signal results in resynchronization of the first programmable counter with respect to a trailing edge of a waveform defining the prescaled signal and the second resynchronization signal results in resynchronization of the second programmable counter with respect to a leading edge of the waveform;

a phase/frequency detector disposed to compare phases between an input reference signal and the frequency-divided signal and to produce a phase error signal;

a charge pump circuit for producing a charge pump signal in response to the phase error signal; and

a loop filter which produces the control voltage in response to the charge pump signal.

7. A phase-locked loop module, comprising:

a voltage-controlled oscillator for generating an output signal of a frequency determined by a control voltage;

a divider circuit for dividing the output signal to produce a frequency-divided signal, the divider including a prescalar circuit configured to produce a prescaled signal by dividing the frequency of the output signal, a first programmable counter and a second programmable counter connected to the output of the prescalar circuit, and a control circuit operatively coupled to the first programmable counter and the second programmable counter, wherein the first programmable counter is characterized by a first effective program counter value of A/2 and the second programmable counter is characterized by a second effective program counter value of B/2 wherein each of A and B may comprise an odd or even integral value, and wherein the control circuit is configured to provide a first resynchronization signal to the first programmable counter and a second resynchronization signal to the second programmable counter and wherein the control circuit further provides, when A is comprised of an even value and B is comprised of an odd value, a sequence of first resynchronization signals to the first programmable counter and a sequence of second resynchronization signals to the second programmable counter wherein successive ones of the first resynchronization signals result in the first programmable counter being resynchronized alternately with respect to leading and trailing edges of a waveform defining the prescaled signal;

a phase/frequency detector disposed to compare phases between an input reference signal and the frequency-divided signal and to produce a phase error signal;

a charge pump circuit for producing a charge pump signal in response to the phase error signal; and

a loop filter which produces the control voltage in response to the charge pump signal.