Cascode circuit and semiconductor device
First Claim
1. A cascode circuit comprising:
- a first N-channel depletion type MOS transistor having a source and a gate connected to each other;
a second N-channel depletion type MOS transistor having a gate connected to the gate of the first N-channel depletion type MOS transistor, for supplying power to a load circuit connected to a source of the second N-channel depletion type MOS transistor; and
a control current source connected to the source of the first N-channel depletion type MOS transistor, the control current source being controlled by current through the load circuit, whereinthe drain-source voltage of the first N-channel depletion type MOS transistor is set to be higher than threshold voltage, and the substrate potential is set to be lower than source potential of the first N-channel depletion type MOS transistor, andthe drain-source voltage of the second N-channel depletion type MOS transistor is set to be higher than threshold voltage, and the substrate potential is set to be lower than source potential of the second N-channel depletion type MOS transistor.
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Accused Products
Abstract
A reference voltage circuit having a high power supply rejection ratio, and can operate at low voltage is provided. The reference voltage circuit includes a bias circuit constructed such that a depletion type transistor (3) is connected in series to a power supply voltage supply terminal of a load circuit, an enhancement type MOS transistor (4) for detecting current through the load circuit to operate as a current source is connected to the load circuit, a depletion type MOS transistor (5) is connected in series to the transistor (4), and a gate terminal of the transistor (5) is connected to a source terminal of the transistor (5), in which the gate terminal of the depletion type transistor (3) is connected to the source terminal of the depletion type transistor (5).
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Citations
19 Claims
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1. A cascode circuit comprising:
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a first N-channel depletion type MOS transistor having a source and a gate connected to each other; a second N-channel depletion type MOS transistor having a gate connected to the gate of the first N-channel depletion type MOS transistor, for supplying power to a load circuit connected to a source of the second N-channel depletion type MOS transistor; and a control current source connected to the source of the first N-channel depletion type MOS transistor, the control current source being controlled by current through the load circuit, wherein the drain-source voltage of the first N-channel depletion type MOS transistor is set to be higher than threshold voltage, and the substrate potential is set to be lower than source potential of the first N-channel depletion type MOS transistor, and the drain-source voltage of the second N-channel depletion type MOS transistor is set to be higher than threshold voltage, and the substrate potential is set to be lower than source potential of the second N-channel depletion type MOS transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor device comprising a cascode circuit, the cascode circuit comprising:
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a first N-channel depletion type MOS transistor having a source and a gate connected to each other; a second N-channel depletion type MOS transistor having a gate connected to the gate of the first N-channel depletion type MOS transistor; a third N-channel depletion type MOS transistor having a drain connected to a source of the second N-channel depletion type MOS transistor, and having a source and a gate connected to each other; a second N-channel enhancement type MOS transistor having a drain connected to the source of the third N-channel depletion type MOS transistor; a first N-channel enhancement type MOS transistor having a drain connected to the source of the first N-channel depletion type MOS transistor; a fourth N-channel depletion type MOS transistor having a gate connected to the gate of the first N-channel depletion type MOS transistor; a fifth N-channel depletion type MOS transistor having a drain connected to a source of the fourth N-channel depletion type MOS transistor, and having a gate connected to the source of the third N-channel depletion type MOS transistor; and a plurality of serially connected resistances connected to the gates of the first and second N-channel enhancement type MOS transistors and to a source of the fifth N-channel depletion type MOS transistor, wherein the cascode circuit is constructed such that positive constant voltage is output from an arbitrary point of connection of the plurality of serially connected resistances, and substrate potentials of all the MOS transistors are grounded. - View Dependent Claims (13, 14, 15)
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16. A semiconductor device comprising a cascode circuit, the cascode circuit comprising:
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a first N-channel depletion type MOS transistor having a source and a gate connected to each other; a second N-channel depletion type MOS transistor having a gate connected to the gate of the first N-channel depletion type MOS transistor; a third N-channel depletion type MOS transistor having a drain connected to a source of the second N-channel depletion type MOS transistor, and having a source and a gate connected to each other; a second N-channel enhancement type MOS transistor having a drain connected to the source of the third N-channel depletion type MOS transistor; a first N-channel enhancement type MOS transistor having a drain connected to the source of the first N-channel depletion type MOS transistor; a fourth N-channel depletion type MOS transistor having a gate connected to the gate of the second N-channel depletion type MOS transistor; a fifth N-channel depletion type MOS transistor having a drain connected to a source of the fourth N-channel depletion type MOS transistor, and having a gate connected to the source of the third N-channel depletion type MOS transistor; and a plurality of serially connected resistances connected to the gates of the first and second N-channel enhancement type MOS transistors and to a source of the fifth N-channel depletion type MOS transistor, wherein the cascode circuit is constructed such that positive constant voltage is output from an arbitrary point of connection of the plurality of serially connected resistances, and substrate potentials of all the MOS transistors are grounded. - View Dependent Claims (17, 18, 19)
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Specification