Microcontroller with programmable logic

• US 7,480,165 B1
• Filed: 04/11/2005
• Issued: 01/20/2009
• Est. Priority Date: 12/16/1997
• Status: Expired due to Fees

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Eric N. Mann
• Inventors: Mann, Eric N.
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US11/103,416
• Time in Patent Office: 1,380 Days
• Field of Search: 365/51, 365/52, 365/63, 326/37, 326/38, 326/39, 326/41
• US Class Current: 365/51
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A programmable logic, a memory and a microcontroller. The memory is coupled to the programmable logic circuit via the microcontroller. The programmable logic circuit, the memory and the microcontroller are fabricated as a single integrated circuit.

Claims

1. A circuit comprising:

a programmable logic circuit comprising one or more macrocells, wherein said one or more of said macrocells comprise a memory section that may be configured as a memory element selected from the group consisting of a D-flip-flop, a T-flip-flop, a latch and a buffer; and

a memory coupled to said programmable logic circuit via a microcontroller, wherein said programmable logic circuit, said memory and said microcontroller are fabricated as a single integrated circuit.

2. The circuit according to claim 1, wherein one or more of said macrocells comprises an input/output macrocell.

3. The circuit according to claim 1, wherein one or more of said macrocells comprises a buried macrocell.

4. The circuit according to claim 2, wherein said one or more of said macrocells comprises an input/output pin.

5. The circuit according to claim 1, wherein said programmable logic circuit is selected from the group consisting of a complex programmable logic device (CPLD) and a programmable logic array (PLA).

6. The circuit according to claim 3, wherein said programmable logic circuit is selected from the group consisting of a complex programmable logic device (CPLD) and a programmable logic array (PLA).

7. The circuit according to claim 1, wherein said memory comprises a read only memory.

8. The circuit according to claim 1, wherein said memory comprises an erasable read only memory.

9. The circuit according to claim 1, wherein said memory comprises an erasable and programmable memory.

10. The circuit according to claim 1, wherein one or more of said macrocells comprises a multiplexor.

11. The circuit according to claim 10, wherein said multiplexor comprises one or more product term inputs and one or more control signals.

12. The circuit according to claim 1, wherein said memory section is configured in response to one or more configuration bits from said memory.

13. A circuit comprising:

a programmable logic circuit; and

a memory coupled to said programmable logic circuit via a microcontroller, wherein said programmable logic circuit, said memory and said microcontroller are fabricated as a single integrated circuit and said memory is connected only to said microcontroller.

14. A circuit comprising:

a programmable logic circuit; and

a memory coupled to said programmable logic circuit via a microcontroller, wherein said programmable logic circuit, said memory and said microcontroller are fabricated as a single integrated circuit and said programmable logic circuit comprises a programmable interconnect matrix that connects one or more of an address, a control and a data out signal to said microcontroller.

15. The circuit according to claim 14, wherein said programmable interconnect matrix provides at least one of a wired AND or a wired OR.

16. The circuit according to claim 14, wherein said programmable interconnect matrix is configured to receive one or more external inputs.

17. The circuit according to claim 14, wherein said programmable logic circuit further comprises one or more input/output macrocells.