Semiconductor memory device

• US 7,480,168 B2
• Filed: 06/28/2007
• Issued: 01/20/2009
• Est. Priority Date: 05/21/2001
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Arimoto, Kazutami, Shimano, Hiroki
• Primary Examiner(s): Yoha; Connie C
• Application Number:
  US11/819,583
• Publication Number:
  US 20080175038A1
• Time in Patent Office: 572 Days
• Field of Search: 365/149, 365/230.06, 365/230.03, 365/189.09
• US Class Current: 365/149
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2211/4013 Memory devices with multiple cells per bit, e.g. twin-cells
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/48 Data lines or contacts therefor

Abstract

Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

Claims

1. A semiconductor memory device, comprising:

a plurality of memory cells arranged in row and columns, each of said memory cells including a capacitor including a cell plate electrode and a storage electrode arranged facing to said cell plate electrode, for accumulating electric charges corresponding to storage data;

a plurality of word lines arranged corresponding to the rows of memory cells and each connecting to the memory cells in a corresponding row, said word lines being formed in a same interconnection layer as the cell plate electrodes;

a plurality of bit lines arranged corresponding to the columns of memory cells and each connecting to the memory cells on a corresponding column, the bit lines being arranged in pairs and bit lines in each pair being arranged with a bit line of other pair interposed in between; and

row selecting circuitry for selecting an addressed word line out of the word lines in accordance with an address signal, the memory cells being arranged such that data in selected memory cells on an addressed row are simultaneously read out onto bit lines in a pair by a selected word line, said row selecting circuitry selecting one word line out of the word lines in accordance with the address signal.

2. The semiconductor memory device according to claim 1, wherein

the memory cells are arranged at alternate bit lines in a row direction, and one of the bit lines adjacent to each other in a same row is provided with a memory cell, and another bit line of said bit lines is provided with no memory cell, and

said semiconductor memory device further comprises:

a plurality of sense amplifiers provided corresponding to the bit line pairs, for amplifying a voltage of a corresponding bit line pair differentially when activated; and

sense amplifier control circuitry for activating a sense amplifier arranged corresponding to a pair of bit lines connected to selected memory cells selectively out of said plurality of sense amplifiers in accordance with said address signal.

3. The semiconductor memory device according to claim 2, wherein said sense amplifiers comprise a group of sense amplifiers arranged corresponding to a first group of the bit line pairs and a second group of sense amplifiers arranged corresponding to a second group of said bit line pairs, and

said sense amplifier control circuitry activates one of the first and second groups of sense amplifiers in accordance with said address signal.

4. The semiconductor memory device according to claim 3, wherein the first sense amplifier group comprises the sense amplifiers arranged at one side of said bit lines in a column direction and the second sense amplifier group comprises the sense amplifiers arranged at another side of said bit lines in said column direction.

5. The semiconductor memory device according to claim 3, wherein said sense amplifier control circuitry selectively activates the first and second sense amplifier groups in accordance with a bank address signal included in said address signal.

6. The semiconductor memory device according to claim 2 wherein said plurality of sense amplifiers are arranged in alignment at one side of the bit line pairs.

7. The semiconductor memory device according to claim 6, wherein said plurality of memory cells are divided into row blocks in a column direction, and

the sense amplifiers are arranged between the row blocks such that the sense amplifiers are shared between the row blocks adjacent thereto, and that with respect to each row block, corresponding sense amplifiers are arranged at only one side of said each row block.

8. The semiconductor memory device according to claim 3, wherein said first and second groups of sense amplifiers are coupled to individual ports accessible independently of each other, respectively.

9. The semiconductor memory device according to claim 3, wherein the sense amplifiers of said first group and the sense amplifiers of said second group are alternately arranged oppositely with respect to the bit line pairs.