Non-volatile memory with background data latch caching during read operations
First Claim
1. A non-volatile memory device having addressable pages of memory cells on associated wordlines, comprising:
- a set of data latches provided for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits;
a state machine for controlling a read operation on a designated group of pages;
said state machine sensing and latching a page of data in each of a series of reading cycles, wherein the sensing and latching in a current reading cycle are directed to a current page of data on a current wordline and are performed responsive to prerequisite data from an adjacent wordline so as to correct for any perturbation effects therefrom;
said state machine preemptively sensing and latching the prerequisite data for the current page prior to the current reading cycle; and
said state machine performing in the current reading cycle, other than the first reading cycle, said sensing and latching of the current page while outputting a previous page sensed and latched in the just passed reading cycle.
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Abstract
Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A scheme for caching read data is implemented so that even when the read for a current page on a current wordline must be preceded by a prerequisite read of data on an adjacent wordline, the prerequisite read along with any I/O access is preemptively done in the cycle for reading a previous page so that the current read can be performed while the previously read page is busy with the I/O access.
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Citations
14 Claims
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1. A non-volatile memory device having addressable pages of memory cells on associated wordlines, comprising:
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a set of data latches provided for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits; a state machine for controlling a read operation on a designated group of pages; said state machine sensing and latching a page of data in each of a series of reading cycles, wherein the sensing and latching in a current reading cycle are directed to a current page of data on a current wordline and are performed responsive to prerequisite data from an adjacent wordline so as to correct for any perturbation effects therefrom; said state machine preemptively sensing and latching the prerequisite data for the current page prior to the current reading cycle; and said state machine performing in the current reading cycle, other than the first reading cycle, said sensing and latching of the current page while outputting a previous page sensed and latched in the just passed reading cycle. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A non-volatile memory device having addressable pages of memory cells on associated wordlines, comprising:
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a set of data latches provided for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits; means for controlling a read operation on a designated group of pages; means for sensing and latching a page of data in each of a series of reading cycles, wherein said means for the sensing and latching in a current reading cycle is directed to a current page of data on a current wordline and is responsive to prerequisite data from an adjacent wordline so as to correct for any perturbation effects therefrom; means for preemptively sensing and latching the prerequisite data for the current page prior to the current reading cycle; and said means for sensing and latching in the current reading cycle, other than the first reading cycle, sensing and latching the current page while outputting a previous page sensed and latched in the just passed reading cycle.
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Specification