Method for low power refresh of a dynamic random access memory using a slower refresh rate than a normal refresh rate

• US 7,480,199 B2
• Filed: 03/30/2007
• Issued: 01/20/2009
• Est. Priority Date: 04/11/2002
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Blodgett, Greg A., Morgan, Donald M.
• Primary Examiner(s): Tran; Andrew Q
• Application Number:
  US11/731,039
• Publication Number:
  US 20070171752A1
• Time in Patent Office: 662 Days
• Field of Search: 365/222, 365/190, 365/230.04, 365/230.06, 365/229, 365/227, 365/228, 365/226, 365/233.15, 365/233.1
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: G11C 2211/4067 Refresh in standby or low power modes
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.

Claims

1. A method of operating a DRAM device in either a high power, full density mode or a low power, reduced density mode, comprising:

reordering each row address applied to the DRAM device by making the N most significant bits of the row address the N least significant bits of a reordered row address, and each of the remaining bits of the row address the next highest order bit of the reordered row address, where N is a positive integer;

when operating in the full density mode, accessing rows of memory cells in an array according to the reordered row address;

when operating in the full density mode, refreshing the memory cells in the array at a first rate;

when operating in the reduced density mode, accessing rows of memory cells in the array according to the reordered row address, and, when accessing each row of memory cells, also accessing 2^N−

1 adjacent rows of memory cells;

when operating in the reduced density mode, refreshing memory cells in the memory array at a second rate that is slower than the first rate; and

when switching from operation in the full density mode to operation in the reduced density mode, transferring data from each row of the array in which data are stored to the 2^N−

1 adjacent rows of memory cells.

2. The method of claim 1 wherein the act of transferring data from each row of the array in which data are stored to the 2^N−

1 adjacent rows of memory cells comprises;

activating a word line for the row in which data are stored thereby coupling each of the memory cells in the row to one of a respective pair of complementary digit lines;

sensing the voltage between each of the complementary pairs of digit lines using a respective sense amplifier that drives the differential voltage between the complementary digit lines to a predetermined voltage; and

while each of the sense amplifiers is driving the predetermined voltage between the respective pair of complementary digit lines, activating respective word lines for the 2^N−

1adjacent rows thereby coupling one of each of the pairs of complementary digit lines to the respective memory cell in the 2^N−

1 adjacent rows.

3. The method of claim 2 wherein the act of activating a word line comprises activating a word line for a specific even-numbered row, and wherein the act of activating a word line for the 2^N−

1 adjacent rows comprises activating 2^N−

1 word lines adjacent the word line for the specific even-numbered row.

4. The method of claim 1 wherein the DRAM device includes a pair of complementary digit lines for each column of the array, and wherein, when operating in the reduced density mode, the act of accessing rows of memory cells in the array according to the reordered row address and accessing the 2^N−

1 adjacent rows of memory cells comprises coupling a memory cell in each column of the accessed row of memory cells to the same digit line to which 2^N−

1 memory cells in 2^N−

1 adjacent rows of memory cells in the same column are coupled.

5. The method of claim 1 wherein the DRAM device includes a pair of complementary digit lines for each column of the array, and wherein, when operating in the reduced density mode, the act of accessing rows of memory cells in the array according to the reordered row address and accessing the 2^N−

1 adjacent rows of memory cells comprises coupling a memory cell in each column of the accessed row of memory cells to a different digit line from which a memory cell in a next adjacent row of memory cells in the same column is coupled.

6. A method of operating a DRAM device, comprising:

reordering row addresses applied to the DRAM device by offsetting row addresses with respective row address offsets so that addresses having sequential row address values correspond to respective rows of memory cells in the DRAM device that are spaced apart from each other by a predetermined number of rows; and

accessing rows of memory cells in a memory array according to the reordered row address.

7. The method of claim 6 wherein the row address offset for each row address comprises a value equal to the respective row address.

8. The method of claim 6 wherein the reordered row addresses have respective even-number values.