Wireless device having a distinct hardware accelerator to support data compression protocols dedicated to GSM (V.42)
First Claim
1. A processor within a wireless terminal operable to perform data compression and decompression according to a data compression protocol, comprising:
- an interface that receives incoming information to be compressed or decompressed according to the data compression protocol;
a processing module operably coupled to the interface;
a data compression/decompression accelerator module operably coupled to the processing module, wherein the data compression/decompression accelerator module includes state machines using a microcoded engine that is reprogrammable by reprogramming an instruction memory associated with the data compression/decompression accelerator module; and
shared memory operably coupled to the processing module and to the data compression/decompression accelerator module, wherein;
the processing module is to store the information in the shared memory for retrieval by the data compression/decompression accelerator module and the processing module to generate an instruction to the data compression/decompression accelerator module that includes a pointer to point to the stored information, the instruction to identify a process to be performed to the stored information, and the instruction further includes multiple conditional branch targets and a fall-through target for the performed process;
the processing module and the data compression/decompression accelerator module are contained within a single Integrated Circuit (IC); and
processing of the information to be compressed or decompressed according to the data compression protocol is performed by the data compression/decompression accelerator module as directed by the processing module and processed information is subsequently returned to the shared memory for retrieval by the processing module.
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Accused Products
Abstract
A processor within a wireless terminal performs data compression, decompression and error correction according to a data compression protocol such as the V.42bis data compression protocol used within GSM wireless networks. This processor includes an interface that receives incoming information or data to be compressed or decompressed according to the data compression protocol. A processing module within the processor is operably coupled to the interface to receive and process the incoming information. Instructions executed within the processing module will divide the processing responsibilities between the processing module and a data compression/decompression accelerator operably coupled to the processing module. Compute intensive operations may be offloaded from the processing module onto the data compression/decompression accelerator to improve overall system efficiency.
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Citations
32 Claims
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1. A processor within a wireless terminal operable to perform data compression and decompression according to a data compression protocol, comprising:
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an interface that receives incoming information to be compressed or decompressed according to the data compression protocol; a processing module operably coupled to the interface; a data compression/decompression accelerator module operably coupled to the processing module, wherein the data compression/decompression accelerator module includes state machines using a microcoded engine that is reprogrammable by reprogramming an instruction memory associated with the data compression/decompression accelerator module; and shared memory operably coupled to the processing module and to the data compression/decompression accelerator module, wherein; the processing module is to store the information in the shared memory for retrieval by the data compression/decompression accelerator module and the processing module to generate an instruction to the data compression/decompression accelerator module that includes a pointer to point to the stored information, the instruction to identify a process to be performed to the stored information, and the instruction further includes multiple conditional branch targets and a fall-through target for the performed process; the processing module and the data compression/decompression accelerator module are contained within a single Integrated Circuit (IC); and processing of the information to be compressed or decompressed according to the data compression protocol is performed by the data compression/decompression accelerator module as directed by the processing module and processed information is subsequently returned to the shared memory for retrieval by the processing module. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A wireless terminal that comprises:
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a Radio Frequency (RF) front end; a baseband processor communicatively coupled to the RF front end that receives incoming information to be compressed or decompressed according to a data compression protocol; a shared memory coupled to the baseband processor to store the information; and a data compression/decompression accelerator module operably coupled to the baseband processor and the shared memory to perform compression or decompression operation on the stored information according to the data compression protocol, wherein the data compression/decompression accelerator module includes state machines using a microcoded engine that is reprogrammable by reprogramming an instruction memory associated with the data compression/decompression accelerator module, in which the baseband processor generates an instruction to the data compression/decompression accelerator module, wherein the instruction includes a pointer to be passed to the data compression/decompression accelerator module to point to the stored information, the instruction to identify a process to be performed to the stored information, and the instruction further includes multiple conditional branch targets and a fall-through target for the performed process, wherein upon completion of the compression or decompression operation, the data compression/decompression accelerator module returns compressed or decompressed information back to the shared memory for retrieval by the baseband processor. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method to process information within a wireless terminal comprising:
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receiving information at a processing engine; determining if a compression or decompression operation is needed in the processing engine; storing the information in a shared memory if compression or decompression operation is needed for retrieval of the information by a data compression/decompression accelerator module; generating an instruction to the data compression/decompression accelerator module from the processing engine, in which the instruction includes a pointer to point to the stored information, the instruction to identify a process to be performed to the stored information, and the instruction further includes multiple conditional branch targets and a fall-through target to perform the process; performing the compression or decompression operation in the data compression/decompression accelerator module that includes state machines using a microcoded engine that is reprogrammable by reprogramming an instruction memory associated with the data compression/decompression accelerator module; storing the compressed or decompressed information in the shared memory; and retrieving the stored compressed or decompressed information by the processing engine. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32)
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Specification