Phase persistent agile signal source method, apparatus, and computer program product

• US 7,480,688 B2
• Filed: 11/30/2005
• Issued: 01/20/2009
• Est. Priority Date: 11/30/2004
• Status: Active Grant

• Current Assignee: AAI Corporation (Textron Inc)
• Original Assignee: AAI Corporation (Textron Inc)
• Inventors: Baummer, Robert J. Jr., Meckley, Jeffrey L., McClelland, William F., McGrath, Thomas P.
• Primary Examiner(s): Do; Chat C
• Application Number:
  US11/289,783
• Publication Number:
  US 20060136537A1
• Time in Patent Office: 1,147 Days
• Field of Search: 708270-277
• US Class Current: 708/271
• CPC Class Codes: G01C 21/3611 using character input or menus, e.g. menus of POIs character input methods in general G06F3/0233
• CPC Class Codes: G01C 21/3614 through interaction with a road map, e.g. selecting a POI icon on a road map
• CPC Class Codes: G01C 21/3617 using user history, behaviour, conditions or preferences, e.g. predicted or inferred from previous use or current movement
• CPC Class Codes: G06F 1/0335 the phase increment itself being a composed function of two or more variables, e.g. frequency and phase
• CPC Class Codes: G08G 1/096861 where the immediate route instructions are output to the driver, e.g. arrow signs for next turn
• CPC Class Codes: G08G 1/0969 having a display in the form of a map

Abstract

A phase persistent agile signal source method, apparatus, and/or computer program product provides a direct digital synthesizer (DDS) clock rate, provides a frequency tuning word (FTW) for a desired output frequency, provides a DDS update for a desired DDS update rate, provides an equivalent frequency least significant bit (LSB) for the desired DDS update rate, provides a current phase of an LSB accumulator, and generates a coherent phase of the desired output frequency based on the DDS clock rate, FTW, DDS update rate to the DDS, equivalent LSB for the desired DDS update rate, and current phase of the LSB accumulator. The coherent phase can be the fraction portion of the result obtained from the multiplication of the FTW and the current phase of the LSB accumulator.

Claims

1. A phase persistent agile signal source method comprising:

providing a direct digital synthesizer (DDS) clock rate;

providing a frequency tuning word (FTW) for a desired output frequency;

providing a DDS update for a desired DDS update rate;

providing an equivalent frequency least significant bit (LSB) for the desired DDS update rate;

providing a current phase of an LSB accumulator; and

generating a coherent phase of the desired output frequency based on at least the DDS clock rate, FTW, DDS update rate to the DDS, equivalent LSB for the desired DDS update rate, and current phase of the LSB accumulator to maintain a time continuous phase of an output signal with the desired output frequency when the DDS is programmed to another output frequency and then back to the desired output frequency.

2. The method according to claim 1, wherein said providing an equivalent frequency step further comprises obtaining the equivalent frequency LSB of the desired DDS update rate by multiplying the LSB of the FTW by the DDS clock rate and dividing by the DDS update rate.

3. The method according to claim 1, wherein said providing a current phase step further comprises adding the current phase of the LSB accumulator to the equivalent frequency LSB for the desired DDS update.

4. The method according to claim 1, wherein said generating a coherent phase step further comprises generating the coherent phase by multiplying the FTW by the current phase of the LSB accumulator and utilizing the fractional portion of the result.

5. The method according to claim 4, wherein said fractional portion of the coherent phase is that portion of the coherent phase that is a fraction of a full cycle where a full cycle is comprised of 360 degrees.

6. A phase persistent agile signal source apparatus comprising:

an equivalent accumulator; and

a direct digital synthesizer (DDS) communicatively connected to the equivalent phase accumulator and having a clock rate,

wherein said phase persistent agile signal source apparatus is configured to operate at a sub-multiple of the clock rate to phase track an output frequency of the DDS to maintain a time continuous phase of an output signal having an output frequency of the DDS when the DDS is programmed to another output frequency and then back to the original frequency, and

wherein said equivalent accumulator further comprises;

a least significant bit (LSB) accumulator a programmable register to program a frequency tuning word; and

provides an equivalent frequency least significant bit;

provides a DDS update rate; and

generates a coherent phase of the LSB accumulator.

7. The apparatus according to claim 6, wherein said LSB accumulator comprises:

addition logic; and

a register to store the current phase at the occurrence of a DDS update for a desired DDS update rate.

8. The apparatus according to claim 7, wherein said addition logic receives an equivalent frequency LSB for the desired DDS update rate.

9. The apparatus according to claim 6, wherein said apparatus is configured to obtain an equivalent frequency least significant bit for a desired DDS update rate by multiplying a least significant bit of the frequency tuning word by a direct digital synthesizer clock rate and dividing by the direct digital synthesizer update rate.

10. The apparatus according to claim 6, wherein said apparatus is configured to add a current phase of the least significant bit accumulator to the equivalent frequency least significant bit for a desired DDS update.

11. The apparatus according to claim 10, wherein the fractional portion of the coherent phase is a portion of the coherent phase that is a fraction of a full cycle where a full cycle is comprised of 360 degrees.

12. The apparatus according to claim 6, wherein said apparatus is configured to generate a coherent phase by multiplying the frequency tuning word by a current phase of the LSB accumulator and utilizing a fractional portion of the result.

13. A computer program product including a computer readable medium with phase persistent agile signal source instructions embodied thereon for carrying out steps comprising:

providing a direct digital synthesizer (DDS) clock rate;

providing a frequency tuning word (FTW) for a desired output frequency;

providing a DDS update for a desired DDS update rate;

providing an equivalent frequency least significant bit (LSB) for the desired DDS update rate;

providing a current phase of an LSB accumulator; and

generating a coherent phase of the desired output frequency based on the DDS clock rate, FTW, DDS update rate to the DDS, equivalent LSB for the desired DDS update rate, and current phase of the LSB accumulator to maintain a time continuous phase of an output signal with the desired output frequency when the DDS is programmed to another output frequency and then back to the desired output frequency.

14. The computer program product according to claim 13, wherein said providing an equivalent frequency step further comprises obtaining the equivalent frequency least significant bit for the desired DDS update rate by multiplying the least significant bit of the FTW by the DDS clock rate and dividing by the DDS update rate.

15. The computer program product according to claim 13, wherein said providing a current phase step further comprises adding the current phase of the LSB accumulator to the equivalent frequency least significant bit for a desired DDS result.

16. The computer program product according to claim 13, wherein said generating a coherent phase step further comprises generating the coherent phase by multiplying the FTW by the current phase of the LSB accumulator and utilizing a fractional portion of the result.

17. The computer program product according to claim 16, wherein the fractional portion of the coherent phase is a portion of the coherent phase that is a fraction of a full cycle where a full cycle is comprised of 360 degrees.

18. The computer program product according to claim 13, further comprising coherent phase algorithm code.

19. The computer program product according to claim 13, further comprising phase coherency simulation code and automatic test bench for phase accumulator code.