Systolic de-multiplexed finite impulse response filter array architecture for linear and non-linear implementations

• US 7,480,689 B2
• Filed: 11/19/2004
• Issued: 01/20/2009
• Est. Priority Date: 11/19/2004
• Status: Expired due to Fees

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Song, William S.
• Primary Examiner(s): Do; Chat C
• Application Number:
  US10/993,076
• Publication Number:
  US 20060112157A1
• Time in Patent Office: 1,523 Days
• Field of Search: 708300-323
• US Class Current: 708/300
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H03H 2220/06 Systolic

Abstract

Described is a finite impulse filter response (FIR) filter for use by signal processors. A demultiplexer receives input data samples at an input data rate. The FIR filter includes a plurality of computational units arranged in a systolic array of taps and phases. Each computational unit operates at an array clock rate that is slower than the input data rate. During each array clock cycle, the phases produce a plurality of output data samples that provides an output data rate equal to the input data rate. The FIR filters can thus support an output data rate equal to the input data rate although the input data rate exceeds the maximum clock speed of the processor. The FIR filter can also operate at a reduced array clock speed, while continuing to produce an output data rate equal to the input data rate, to increase the power efficiency of the processor.

Claims

1. A signal processor circuit, comprising:

a demultiplexer circuit receiving input data samples at an input data rate; and

a finite impulse response (FIR) filter circuit in communication with the demultiplexer circuit for obtaining the input data samples therefrom at the input data rate, the FIR filter circuit including a plurality of computational unit circuits arranged in an array having a plurality of taps and a plurality of phases, each computational unit circuit including circuitry that receives some of the input data samples obtained from the demultiplexer circuit and computes values based on these received input data samples at an array clock rate that is slower than the input data rate, wherein during each array clock cycle the demultiplexer circuit forwards input data samples concurrently to each phase and to each tap of computational unit circuits.

2. The signal processor circuit of claim 1, wherein the array has N phases, where N is any integer greater than 1, and wherein the array clock rate at which each computational unit circuit computes values is approximately equal to 1/N of the input date rate.

3. The signal processor circuit of claim 1,wherein the plurality of phases produces during each array clock cycle a plurality of output data samples that provides an output data rate equal to the input data rate.

4. The signal processor circuit of claim 1,wherein the plurality of phases produces during each array clock cycle a plurality of output data samples that provides an output data rate that is greater than the input data rate.

5. The signal processor circuit of claim 1, wherein the plurality of phases produces during each array clock cycle an output data rate that is less than the input data rate.

6. The signal processor circuit of claim 1, further comprising a set of coefficients with each coefficient in the set being associated with one of the taps of the FIR filter circuit, each computational unit circuit of a given tap using the coefficient associated with that tap to multiply an input data sample received by that computational unit circuit.

7. The signal processor circuit of claim 6, wherein each coefficient in the set is different from each of the other coefficients in the set.

8. The signal processor circuit of claim 1, wherein the demultiplexer circuit forwards input data samples to the phases of computational unit circuits according to a round robin sequence.

9. A finite impulse response (FIR) filter circuit for filtering input data samples, the FIR filter circuit comprising a plurality of computational unit circuits arranged in a systolic array having a plurality of columns and a plurality of rows, each column of computational unit circuits corresponding to one of a tap and a phase and each row of computational unit circuits corresponding to the other of a tap and a phase, each computational unit circuit in one phase other than a last phase being in communication with a first computational unit circuit in a neighboring tap within the same phase as that computational unit circuit over a first signal line used to communicate a computed value thereto and with a second computational unit circuit in the neighboring tap and in a neighboring phase over a second signal line used to communicate an input data sample thereto, each tap and each phase of the systolic array being adapted to receive concurrently an input data sample from a demultiplexer during each array clock cycle.

10. The FIR filter circuit of claim 9, wherein the array has N phases, where N is any integer greater than 1, each computational unit circuit operates at an array clock rate that is equal to 1/N of an input data rate of the input data samples, and the plurality of phases of computational unit circuits produces during each array clock cycle an output data rate equal to the input data rate.

11. The FIR filter circuit of claim 9, wherein the array has N phases, where N is any integer greater than 1, each computational unit circuit operates at an array clock rate that is equal to 1/N of an input data rate of the input data samples, and the plurality of phases of computational unit circuits produces during each array clock cycle an output data rate that is less than the input data rate.

12. The FIR filter circuit of claim 9, wherein the array has N phases, where N is any integer greater than 1, each computational unit circuit operates at an array clock rate that is slower than an input data rate of the input data samples, and the plurality of phases of computational unit circuits produces during each array clock cycle an output data rate that is greater than the input data rate.

13. The FIR filter circuit of claim 9, further comprising a set of coefficients, each coefficient in the set being associated with one of the taps of the FIR filter, each computational unit circuit of a given tap using the coefficient associated with that tap to multiply an input data sample received by that computational unit circuit.

14. The FIR filter circuit of claim 13, wherein each coefficient in the set is different from each of the other coefficients in the set.

15. A finite impulse response (FIR) filter circuit for filtering input data samples, comprising:

a plurality of computational unit circuits arranged in a systolic array having a plurality of columns and a plurality of rows, each column of computational unit circuits corresponding to one of a tap and a phase and each row of computational unit circuits corresponding to the other of a tap and a phase, each tap and each phase of the systolic array being adapted to receive concurrently an input data sample from a demultiplexer during each array clock cycle, each computational unit circuit in a tap other than a last tap comprising;

a first input signal line for receiving an input data sample,

a second input signal line for receiving a coefficient,

a third input signal line for receiving a supplied value,

circuitry for computing a value based on the received input data sample, the coefficient, and the supplied value,

a first output signal line for communicating the value computed by that computational unit circuit to a computational unit circuit in a neighboring tap, and

a second output signal line for communicating the received input data sample to a computational unit circuit in a neighboring phase of the neighboring tap.

16. The FIR filter circuit of claim 15, wherein the array has N phases, where N is any integer greater than 1, each computational unit circuit operates at an array clock rate that is equal to 1/N of an input data rate of the input data samples, and the plurality of rows of computational unit circuits produces during each array clock cycle an output data rate equal to the input data rate.

17. The FIR filter circuit of claim 15, wherein the array has N phases, where N is any integer greater than 1, each computational unit circuit operates at an array clock rate that is equal to 1/N of an input data rate of the input data samples, and the plurality of phases of computational unit circuits produces during each array clock cycle an output data rate that is less than the input data rate.

18. The FIR filter circuit of claim 15, wherein the array has N phases, where N is any integer greater than 1, each computational unit circuit operates at an array clock rate that is slower than an input data rate of the input data samples, and the plurality of phases of computational unit circuits produces during each array clock cycle an output data rate that is greater than the input data rate.

19. The FIR filter circuit of claim 15, further comprising a delay circuit disposed between the first input signal line and the second output signal line for holding an input data sample for an array clock cycle before that input data sample passes to the computational unit circuit in the neighboring phase and neighboring tap.

20. The FIR filter circuit of claim 15, further comprising a set of coefficients with each coefficient in the set being associated with one of the taps of the FIR filter circuit, each computational unit circuit of a given tap using the coefficient associated with that tap to multiply an input data sample received by that computational unit circuit.

21. The FIR filter circuit of claim 20, wherein each coefficient in the set is different from each of the other coefficient in the set.

22. A signal processor circuit, comprising:

a demultiplexer circuit receiving input data samples; and

a first finite impulse response (FIR) filter circuit in communication with the demultiplexer circuit for obtaining the input data samples therefrom, the first FIR filter circuit including a first plurality of computational unit circuits arranged in an array having a plurality of taps and a plurality of phases and a first set of coefficients used by the first plurality of computational unit circuits to compute values based on the input data samples; and

a second FIR filter circuit in communication with the demultiplexor circuit for obtaining the input data samples therefrom, the second FIR filter circuit including a second plurality of computational unit circuits arranged in an array having a plurality of taps and a plurality of phases and a second set of coefficients different from the first set of coefficients, the second set of coefficients being used by the second plurality of computational unit circuits to compute values based on the input data samples,

wherein at least one of the computational unit circuits in a last phase of the second FIR filter circuit is in communication with one of the computational unit circuits in a first phase of the first FIR filter circuit for communicating an input data sample thereto during each array clock cycle, and wherein during each array clock cycle the demultiplexer circuit forwards input data samples concurrently to each tap and to each phase of computational unit circuits.

23. The signal processor of claim 22, wherein the first FIR filter circuit receives the input data samples from the demultiplexer circuit one array clock cycle after the second FIR filter circuit receives the input data samples.

24. The signal processor of claim 22, wherein the demultiplexer circuit receives the input data samples at an input data rate and wherein each computational unit circuit in the first and second FIR filter circuits operates at an array clock rate that is slower than the input data rate, the plurality of phases of computational unit circuits of the FIR filter circuits producing during each array clock cycle an output data rate equal to the input data rate.

25. The signal processor of claim 22, wherein the demultiplexor circuit receives the input data samples at an input data rate and wherein each computational unit circuit in the first and second FIR filter circuits operates at an array clock rate that is slower than the input data rate, the plurality of phases of computational unit circuits of the FIR filter circuits producing during each array clock cycle an output data rate that is less than the input data rate.

26. The signal processor of claim 22, wherein the demultiplexer circuit receives the input data samples at an input data rate and wherein each computational unit circuit in the first and second FIR filter circuits operates at an array clock rate that is slower than the input data rate, the plurality of phases of computational unit circuits of the FIR filter circuits producing during each array clock cycle an output data rate that is greater than the input data rate.

27. The signal processor of claim 22, wherein the demultiplexor circuit forwards input data samples to the phases of computational unit circuits according to a round robin sequence.

28. The FIR filter circuit of claim 22, wherein each coefficient in the first and second sets of coefficients is different from each of the other coefficients in the first and second sets of coefficients.

29. A method of linearly filtering input data samples, compnsing:

receiving at a demultiplexer circuit input data samples at an input data rate;

forwarding by the demultiplexer circuit the input data samples concurrently to a first tap and a first phase of an array of computational unit circuits of a finite impulse filter (FIR) circuit having a plurality of taps and a plurality of phases; and

receiving by the computational unit circuits the input data samples forwarded by the demultiplexer circuit and computing values based on these received input data samples at an array clock rate that is slower than the input data rate.

30. The method of claim 29, further comprising producing by the plurality of phases an output data rate that is equal to the input data rate during each array clock cycle.

31. The method of claim 29, further comprising producing by the plurality of phases an output data rate that is greater than the input data rate during each array clock cycle.

32. The method of claim 29, further comprising producing by the plurality of phases an output data rate that is less than the input data rate during each array clock cycle.

33. The method of claim 29, wherein the step of producing comprises:

receiving by each tap of computational unit circuits a plurality of input data samples;

computing by each computational unit circuit a value based on an input data sample received by that computational unit circuit;

communicating by each tap of computational unit circuits other than a last tap the values computed by those computational unit circuits to the computational unit circuits in a neighboring tap;

communicating by each tap of computational unit circuits other than a last tap input data samples received by those computational unit circuits during a previous array clock cycle to the computational unit circuits in a neighboring phase in the neighboring tap;

communicating by the last tap of computational unit circuits a plurality of computed values corresponding to the output data samples.

34. The method of claim 29, further comprising multiplying input data samples received by the computational unit circuits in a given tap by the same coefficient.

35. The method of claim wherein the step of forwarding includes forwarding the input data samples to the computational unit circuits in the first tap of the array in accordance with a round robin sequence.