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Systolic de-multiplexed finite impulse response filter array architecture for linear and non-linear implementations

  • US 7,480,689 B2
  • Filed: 11/19/2004
  • Issued: 01/20/2009
  • Est. Priority Date: 11/19/2004
  • Status: Expired due to Fees
First Claim
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1. A signal processor circuit, comprising:

  • a demultiplexer circuit receiving input data samples at an input data rate; and

    a finite impulse response (FIR) filter circuit in communication with the demultiplexer circuit for obtaining the input data samples therefrom at the input data rate, the FIR filter circuit including a plurality of computational unit circuits arranged in an array having a plurality of taps and a plurality of phases, each computational unit circuit including circuitry that receives some of the input data samples obtained from the demultiplexer circuit and computes values based on these received input data samples at an array clock rate that is slower than the input data rate, wherein during each array clock cycle the demultiplexer circuit forwards input data samples concurrently to each phase and to each tap of computational unit circuits.

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