Electronic data processing circuit that transmits packed words via a bus
First Claim
1. An electronic data processing circuit, the circuit comprisinga plurality of data handling units with data outputs, at least part of the data handling units having address outputs;
- a bus with address lines and data lines, the data lines supporting simultaneous transfer of up to a maximum number of bits in a bus cycle;
a bus controller coupled to the data handling units and arranged to control access to the bus in successive access cycles, the bus controller being arranged to cause data bits from a plurality of data words of less than said maximum number of bits, from respective ones of the data handling units, to be placed in combination on the data lines in a same bus cycle, the bus controller causing write addresses that the respective ones of the data handling units supply for respective ones of the plurality of data words to be placed on the address lines in a plurality of respective bus cycles, corresponding to a position said data word is placed on the data lines.
1 Assignment
0 Petitions
Accused Products
Abstract
An electronic data processing circuit contains a plurality of data handling units (10a-d, 16a-b) with data outputs, at least part of the data handling units having address outputs. The data handling units supply words of preferably selectable size to a bus. A bus controller (20) is arranged to control access to the bus in successive access cycles. The bus controller (20) causes data bits from a plurality of data words from respective ones of the data handling units (10a-d, 16a-b), to be placed in combination on the data lines in a same bus cycle. The bus controller causes write addresses that the respective ones of the data handling units (10a-d, 16a-b) supply for respective ones of the plurality of data words to be placed on the address lines in a plurality of respective bus cycles. Preferably, the temporal or spatial arrangement of the data words on the bus lines adapted so as to minimize the number of logic level changes on the bus.
-
Citations
13 Claims
-
1. An electronic data processing circuit, the circuit comprising
a plurality of data handling units with data outputs, at least part of the data handling units having address outputs; -
a bus with address lines and data lines, the data lines supporting simultaneous transfer of up to a maximum number of bits in a bus cycle; a bus controller coupled to the data handling units and arranged to control access to the bus in successive access cycles, the bus controller being arranged to cause data bits from a plurality of data words of less than said maximum number of bits, from respective ones of the data handling units, to be placed in combination on the data lines in a same bus cycle, the bus controller causing write addresses that the respective ones of the data handling units supply for respective ones of the plurality of data words to be placed on the address lines in a plurality of respective bus cycles, corresponding to a position said data word is placed on the data lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. An electronic data processing circuit, the circuit comprising
a plurality of data handling units with data outputs, at least part of the data handling units having and address outputs for writing words of data; -
a bus with address lines and data lines; a bus controller coupled to the data handling units and arranged to control access to the bus in successive access cycles, the bus controller being arranged to select a distribution and placement of said data words from the data handling units on the data lines of the bus, dependent on an evaluation that takes account of a number of data lines that will change logic level upon placing the words on the data lines, the bus controller selecting a distribution that minimizes the number of data lines that will change logic level among at least two possible distributions. - View Dependent Claims (10, 11)
-
-
12. A method of processing data, the method comprising
supplying a plurality of data words with variable word size and addresses for those data words; -
placing data bits from the plurality of data words of less than the maximum word size on data lines of a bus in a same bus cycle if more than one of the plurality of data words has a word size of less than the maximum word size; placing the addresses for respective ones of the plurality of data words on address lines of the bus in a plurality of respective bus cycles.
-
-
13. A method of processing data, the method comprising
supplying respective data words for output on data lines of a bus; -
selecting distribution of the data words over the data lines and/or over a temporal sequence in which the data words will be placed on the bus, taking account of a number of data lines whose logic level will change upon placing the data words on the data lines, the distribution being selected to minimize the number of data lines that will change logic level among at least two possible distributions; placing the data words on the data lines of the bus according to the selected distribution.
-
Specification