Controller communications over an always-on controller interconnect
First Claim
1. A disk array comprising:
- at least two controller pairs, each controller pair having a first controller coupled to a second controller through a mirror bus, wherein each bus is divided into a first half and a second half;
a controller loop coupling all controllers through a plurality of loop buses;
a first interconnect to which each controller is operatively coupled, the first interconnect carrying the first half of each bus; and
a second interconnect to which each controller is operatively coupled, the second interconnect carrying the second half of each bus.
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Accused Products
Abstract
A controller interconnect structure within a RAID disk array enables continuous low latency/high bandwidth communications between a plurality of controller pairs within the array. Mirror buses carry high speed mirror traffic between mirrored controllers performing mirrored memory operations. Loop buses carry inter-processor communications and other traffic between controller pairs coupled together in a controller loop. Benefits of the interconnect structure include an ability to support continued controller communications and online disk array operations under various failure and repair conditions that might otherwise render a disk array inoperable. In addition, the controller interconnect structure provides for easy expansion of the number of controllers within disk arrays as arrays continue to be scaled up in size to meet increasing storage demands from user host systems.
17 Citations
25 Claims
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1. A disk array comprising:
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at least two controller pairs, each controller pair having a first controller coupled to a second controller through a mirror bus, wherein each bus is divided into a first half and a second half; a controller loop coupling all controllers through a plurality of loop buses; a first interconnect to which each controller is operatively coupled, the first interconnect carrying the first half of each bus; and a second interconnect to which each controller is operatively coupled, the second interconnect carrying the second half of each bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A controller interconnect structure in a disk array comprising:
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a plurality of controllers; a plurality of communications buses operatively coupling the plurality of controllers to one another, each communications bus partitioned into a first half and a second half; a first interconnect to which each of the plurality of controllers is coupled, the first interconnect conveying the first half of the plurality of communications buses; and a second interconnect to which each of the plurality of controllers is coupled, the second interconnect conveying the second half of the plurality of communications buses. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A processor-readable medium comprising processor-executable instructions configured for:
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determining a destination controller pair for a data packet based on a host address for the data packet and an array mapping of the host address to an array address; initially sending the data packet over a controller loop toward the destination controller pair in a first direction determined by a data header and a routing instruction; detecting a failure in the controller loop; rerouting the data packet in a second direction toward the destination controller pair; based on the failure, reprogramming a routing register with new routing information; based on the new routing information, initially sending additional data packets in a direction over the controller loop that avoids the failure; sharing failure information with all controllers; and based on the failure information, reprogramming routing registers on each controller with new routing information. - View Dependent Claims (18)
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19. A processor-readable medium comprising processor-executable instructions configured for:
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receiving at a first controller in a first controller level, data that is destined for a second level controller pair located in a second controller level; sending the data over a first level controller loop to a first level controller pair that corresponds to the second level controller pair; and further sending the data from the first level controller pair to the second level controller pair via a loop bus that couples the first controller level to the second controller level. - View Dependent Claims (20, 21, 22)
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23. A processor-readable medium comprising processor-executable instructions configured for:
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receiving data at a first controller in a first controller level; sending the data from the first controller to a second level controller pair via a loop bus that couples the first controller level to a second controller level; and further sending the data over a second level controller loop to a destination controller pair in the second controller level.
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24. A method of routing data between controller pairs in a multi-controller disk array comprising:
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receiving at a first controller in a first controller level, data that is destined for a second level controller pair located in a second controller level; sending the data over a first level controller loop to a first level controller pair that corresponds to the second level controller pair; and further sending the data from the first level controller pair to the second level controller pair via a loop bus that couples the first controller level to the second controller level.
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25. A method of routing data between controller pairs in a multi-controller disk array comprising:
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receiving data at a first controller in a first controller level; sending the data from the first controller to a second level controller pair via a loop bus that couples the first controller level to a second controller level; and further sending the data over a second level controller loop to a destination controller pair in the second controller level.
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Specification