Substrate noise tool
First Claim
1. A method for analyzing the substrate noise of an integrated circuit at any point during the design cycle, wherein said integrated circuit comprises a plurality of standard cells, comprising:
- creating a noise macrocell for each of said standard cells, wherein the plurality of created noise macrocells comprises a noise model;
simulating said integrated circuit to generate an event model;
creating a model of said substrate, by performing the steps of;
receiving from a user an estimated die size and a substrate resistivity;
dividing said die size into equal sized partitions;
assuming equal distribution of substrate contacts between said partitions;
calculating the resistance between each pair of partitions based on the distance between said pair and said inputted resistivity; and
creating a resistive mesh network using said calculated resistances; and
simulating said substrate model and said noise model using said event model to create a profile of said substrate noise.
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Accused Products
Abstract
System and method for analyzing substrate noise is disclosed, which is capable of accepting inputs of increasing complexity and granularity. During the early phases, the tool can accept coarse circuit descriptions, such as gate level netlists. The tool is capable of generating rudimentary substrate models based on estimated die size, allowing the designer to have an early indication of potential substrate noise issues. During the middle phases, the tool can accept more accurate circuit descriptions, such as a SPICE netlist. A more detailed substrate model can be generated, which considers layout information, thereby allowing the designer to make layout and circuit modifications before the circuit is completed. Lastly, during final verification, the tool can accept an even more accurate netlist, such as a SPICE netlist that includes parasitic capacitance. The tool can also accept a more detailed substrate model and provides the substrate noise analysis necessary to finalize the design.
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Citations
12 Claims
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1. A method for analyzing the substrate noise of an integrated circuit at any point during the design cycle, wherein said integrated circuit comprises a plurality of standard cells, comprising:
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creating a noise macrocell for each of said standard cells, wherein the plurality of created noise macrocells comprises a noise model; simulating said integrated circuit to generate an event model; creating a model of said substrate, by performing the steps of; receiving from a user an estimated die size and a substrate resistivity; dividing said die size into equal sized partitions; assuming equal distribution of substrate contacts between said partitions; calculating the resistance between each pair of partitions based on the distance between said pair and said inputted resistivity; and creating a resistive mesh network using said calculated resistances; and simulating said substrate model and said noise model using said event model to create a profile of said substrate noise. - View Dependent Claims (2, 3)
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4. A system for analyzing the substrate noise of an integrated circuit at any point during the design cycle, wherein said integrated circuit comprises a plurality of standard cells, said system comprising:
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a computer readable device; and
computer executable instructions stored on said device, comprising;means for creating a noise macrocell for each of said standard cells wherein the plurality of created noise macrocells comprises a noise model; means for simulating said integrated circuit to generate an event model; means for creating a model of said substrate, comprising means for receiving from a user an estimated die size and a substrate resistivity; means for dividing said die size into equal sized partitions; means for assuming equal distribution of substrate contacts between said partitions; means for calculating the resistance between each pair of partitions based on the distance between said pair and said inputted resistivity; and means for creating a resistive mesh network using said calculated resistances; and means for simulating said substrate model and said noise model using said event model to create a profile of said substrate noise. - View Dependent Claims (5, 6)
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7. A method for analyzing the substrate noise of an integrated circuit at any point during the design cycle, wherein said integrated circuit comprises a plurality of standard cells, comprising:
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creating a noise macrocell for each of said standard cells, wherein the plurality of created noise macrocells comprises a noise model; simulating said integrated circuit to generate an event model; creating a model of said substrate, by performing the steps of; inputting a circuit layout and the substrate resistivity; determining the location of each substrate contact based on said layout; calculating the resistance between each pair of substrate contacts based on the distance between said pair and said inputted resistivity; and creating a resistive mesh network using said calculated values; and simulating said substrate model and said noise model using said event model to create a profile of said substrate noise. - View Dependent Claims (8, 9)
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10. A system for analyzing the substrate noise of an integrated circuit at any point during the design cycle, wherein said integrated circuit comprises a plurality of standard cells, said system comprising:
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a computer readable device; and
computer executable instructions stored on said device, comprising;means for creating a noise macrocell for each of said standard cells wherein the plurality of created noise macrocells comprises a noise model; means for simulating said integrated circuit to generate an event model; means for creating a model of said substrate, comprising; means for inputting a circuit layout and the substrate resistivity; means for determining the location of each substrate contact based on said layout; means for calculating the resistance between each pair of substrate contacts based on the distance between said pair and said inputted resistivity; and means for creating a resistive mesh network using said calculated values; and means for simulating said substrate model and said noise model using said event model to create a profile of said substrate noise. - View Dependent Claims (11, 12)
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Specification