Semiconductor device having deep trench charge compensation regions and method

• US 7,482,220 B2
• Filed: 10/19/2006
• Issued: 01/27/2009
• Est. Priority Date: 02/15/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Loechelt, Gary H., Grivna, Gordon M., Parsey, John M. Jr., Zdebel, Peter J.
• Primary Examiner(s): Tran; Long K
• Application Number:
  US11/582,889
• Publication Number:
  US 20070034947A1
• Time in Patent Office: 831 Days
• Field of Search: 257/328, 257/339, 257/341, 257/342, 257/E21.418, 257/E29.257, 257/133, 257/139, 257/140, 257/146, 257/147, 257/162, 257/E29.013, 257/E29.174, 257/E29.243, 257/E29.26, 257/E21.016, 257/E21.019, 257/E21.558, 438/227, 438/269, 438/270, 438/289, 438/386
• US Class Current: 438/227
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.

Claims

1. A method of forming a semiconductor device comprising the steps of:

providing a body of semiconductor material having first and second opposing major surfaces;

forming a trench in the body of semiconductor material;

forming a first semiconductor layer of a first conductivity type adjoining surfaces of the trench;

forming a second semiconductor layer of a second conductivity type adjacent to the first semiconductor layer to form a charge compensating trench region;

forming a first doped region in the body of semiconductor material adjacent the charge compensating trench region, wherein the first doped region comprises the second conductivity type;

forming a second doped region in the first doped region and comprising the first conductivity type;

forming a control electrode adjacent the first and second doped regions;

forming a first intrinsic semiconductor layer between the first and second semiconductor layers; and

forming a conductive layer coupled to the charge compensating trench region.

2. The method of claim 1 wherein the step of forming the control electrode comprises forming a spacer gate structure.

3. The method of claim 1 further comprising the step of forming a passivation layer overlying the second semiconductor layer.

4. The method of claim 3, wherein the step of forming the passivation layer comprises forming an oxide layer.

5. The method of claim 3, wherein the step of forming the passivation layer comprises forming a dry oxide layer.

6. The method of claim 3, wherein the step of forming the passivation layer comprises forming a nitride layer.

7. The method of claim 3, wherein the step for forming the passivation layer comprises forming an oxide layer and a nitride layer.

8. The method of claim 3 further comprising the step of forming a void in the charge compensating trench region.

9. A method for forming a semiconductor device comprising the steps of:

providing a body of semiconductor material; and

forming a trench in the body of semiconductor material forming a first layer comprising a single crystal semiconductor material overlying surfaces of the trench, wherein the first layer comprises a first conductivity type;

forming a first intrinsic layer overlying the first layer;

forming a second layer comprising a single crystal semiconductor material overlying the first intrinsic layer, wherein the second layer comprises a second conductivity type, and wherein the first intrinsic layer is configured to reduce intermixing of dopants between the first and second layers;

forming a passivation layer overlying the second layer to form a charge compensation region; and

forming a conductive layer coupled to the charge compensating trench region.

10. The method of claim 9, wherein the step of forming the passivation layer includes forming the passivation layer while leaving a void within the trench.

11. The method of claim 9, wherein the step of forming the passivation layer includes forming a dry oxide layer.