Conformal nanolaminate dielectric deposition and etch bag gap fill process

• US 7,482,247 B1
• Filed: 09/19/2006
• Issued: 01/27/2009
• Est. Priority Date: 12/30/2004
• Status: Active Grant

• Current Assignee: Novellus Systems Incorporated (LAM Research Corporation)
• Original Assignee: Novellus Systems Incorporated (LAM Research Corporation)
• Inventors: Archer, Timothy M., Rulkins, Ron, Somekh, Sasson Roger, Lu, Brian G., Papasouliotis, George D., Yau, Wai-Fan, Hausmann, Dennis M., Nie, Bunsen, Tipton, Adrianne K., Tobin, Jeff, Tarafdar, Raihan M.
• Primary Examiner(s): Fourson; George
• Application Number:
  US11/524,502
• Time in Patent Office: 861 Days
• Field of Search: 438/437, 438/789, 438/FOR.227, 257/E21.245, 257/E21.546
• US Class Current: 438/437
• CPC Class Codes: C23C 16/045 Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
• CPC Class Codes: C23C 16/44 characterised by the method of coating C23C16/04 takes precedence
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02214 the compound comprising silicon and oxygen
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/31608 Deposition of SiO2 H01L21/31625, H01L21/31629 and H01L21/31633 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76837 Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics

Abstract

Conformal nanolaminate dielectric deposition and etch back processes that can fill high aspect ratio (typically at least 5:1, for example 6:1), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of voids or weak spots involve the use of any suitable confirmal dielectric deposition technique and a dry etch back. The etch back part of the process involves a single step or an integrated multi-step (for example, two-step) procedure including an anisotropic dry etch followed by an isotropic dry etch. The all dry deposition and etch back process in a single tool increases throughput and reduces handling of wafers resulting in more efficient and higher quality nanolaminate dielectric gap fill operations.

Claims

1. A method of filling a gap on a semiconductor substrate, the method comprising:

(a) partially filling the gap with a dielectric using a conformal deposition process;

(b) partially removing dielectric deposited in the gap from the gap opening and sidewalls by an etch back process comprising an isotropic dry etch, wherein the etch back process comprises a passivation operation after the etch is complete; and

(c) further filling the partially filled gap by the conformal deposition process.

2. The method of claim 1, wherein the conformal deposition process comprises:

a. exposing the substrate surface to a catalyst or catalyst-containing precursor gas to form a saturated layer of catalyst on the substrate surface; and

b. exposing the substrate surface to a silicon-containing precursor gas to form a dielectric film layer.

3. The method of claim 2, wherein the catalyst or catalyst-containing precursor is a metal catalyst-containing precursor is selected from the list of metal catalyst-containing precursors comprising aluminum, zirconium, hafnium, gallium, titanium, niobium, tantalum, and combinations thereof.

4. The method of claim 3, wherein the metal catalyst-containing precursor is at least one of hexakis(dimethylamino) aluminum and trimethyl aluminum.

5. The method of claim 2, wherein the catalyst or catalyst-containing precursor is a metal- and metalloid-free catalyst that can sufficiently adsorb onto or react with the substrate surface and prepare it to react with the subsequently added silicon-containing precursor to form a dielectric layer more than a monolayer thick.

6. The method of claim 5, wherein the catalyst is selected from the group consisting of organic acids, anhydrides of organic acids, dialkylphosphates, alkysphosphates, phosphonic acids, phosphinic acids, phosphorus oxides, alkylamines (primary, secondary or tertiary), arylamines, alky/arylboronic acids, sulphonic acids, water, ammonium salts, phosphonitrile compounds, boron triflates, inorganic acids, anhydrides of inorganic acids, and combinations thereof.

7. The method of claim 1, wherein the silicon-containing precursor is at least one of a silanol and a silanediol.

8. The method of claim 1, wherein (a) is performed with a process gas mixture comprising a silanol, nitrogen, ozone, and an inert gas.

9. The method of claim 1, wherein the silicon-containing precursor is at least one of tris(tert-butoxy)silanol ((C₄H₉O)₃SiOH) and tris(tert-pentoxy)silanol ((C₅H₁₁O)₃SiOH).

10. The method of claim 1, wherein the conformal dielectric is undoped silicon oxide nanolaminate.

11. The method of claim 1, wherein the conformal dielectric is doped silicon oxide nanolaminate.

12. The method of claim 11, wherein the doped silicon oxide nanolaminate comprises one selected from the group consisting of FSG, PSG, BPSG, and combinations thereof.

13. The method of claim 1, wherein (b) is initiated when the partial filling of the gap is such that the gap opening is no less than about 40% of its initial width.

14. The method of claim 1, wherein the etch back process comprises a single step downstream plasma isotropic etch.

15. The method of claim 1, wherein the etch back process comprises a single step direct plasma partially isotropic etch.

16. The method of claim 1, wherein the etch back process comprises a multi-step etch back process comprising an anisotropic dry etch followed by the isotropic dry etch.

17. The method of claim 1, wherein the dry etch back process conducted in a dual source plasma reactor process chamber comprising an RF source used to generate a plasma for an anisotropic reactive ion etch in the reactor process chamber and a downstream plasma source selected from the group consisting of a microwave source and an inductively coupled plasma source used to generate a plasma for an isotropic reactive ion etch in the reactor process chamber.

18. The method of claim 1, wherein the isotropic etch is selective to the dielectric relative to an underlying gap liner.

19. The method of claim 1, wherein the etch is stopped before corners of elements forming the gap are exposed.

20. The method of claim 1, wherein the etch is preferential for dielectric towards the top of the gap.

21. The method of claim 1, wherein the passivation operation comprises exposing the substrate to a reactive plasma that scavenges remaining etchant gases and byproducts.

22. The method of claim 21, wherein the passivation operation comprises exposing the substrate to a high density plasma comprising a hydrogen-containing gas.

23. The method of claim 20, wherein a partially-filled gap profile having a wider entry than bottom results from the etch.

24. The method of claim 1, wherein the deposition is conducted in a chemical vapor deposition reactor process chamber.

25. The method of claim 1, wherein the deposition and etch back steps are conducted in a single semiconductor processing device with multiple reactor chambers.

26. The method of claim 1, wherein (b) and (c) are repeated until the gap is filled.

27. The method in claim 1, wherein the gap is a feature selected from the group consisting of shallow trench isolation (STI), inter-metal dielectric (IMD), inter-level dielectric (ILD), and pre-metal dielectric (PMD) features in the partially fabricated semiconductor wafer.