Chip structure and process for forming the same

• US 7,482,259 B2
• Filed: 02/02/2008
• Issued: 01/27/2009
• Est. Priority Date: 12/13/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Primary Examiner(s): ZARNEKE, DAVID A
• Application Number:
  US12/025,000
• Publication Number:
  US 20080146019A1
• Time in Patent Office: 360 Days
• Field of Search: None
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05657 Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 27/0248 : for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

Claims

1. A method for fabricating a chip, comprising:

providing a wafer comprising a silicon substrate, a transistor in or on said silicon substrate, a first copper layer over said silicon substrate, a second copper layer over said first copper layer and over said silicon substrate, a dielectric layer between said first and second copper layers, a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers, a first conductive pad over said silicon substrate, a second conductive pad over said silicon substrate, a passivation layer over said first and second copper layers and over said dielectric layer, wherein said passivation layer comprises a nitride, and wherein a first opening in said passivation layer is over said first conductive pad and exposes said first conductive pad, and a second opening in said passivation layer is over said second conductive pad and exposes said second conductive pad, wherein said first opening has a width between 0.5 and 20 micrometers, and a first polymer layer on said passivation layer, wherein a third opening in said first polymer layer is over said first conductive pad and exposes said first conductive pad, and a fourth opening in said first polymer layer is over said second conductive pad and exposes said second conductive pad, and wherein said first polymer layer has a thickness between 1 and 100 micrometers and greater than that of said passivation layer, wherein said first polymer layer is formed by a process comprising spin coating a photosensitive material, and wherein said third and fourth openings are formed by a process comprising a photolithography process; and

forming a metallization structure over said wafer, on said first polymer layer and on said first and second conductive pads, wherein said first conductive pad is connected to said second conductive pad through said metallization structure, and wherein said forming said metallization structure comprises forming a metal layer on said first polymer layer and on said first and second conductive pads, wherein said forming said metal layer comprises a sputtering process, followed by forming a photoresist layer on said metal layer, wherein a fifth opening in said photoresist layer exposes said metal layer, followed by electroplating a third copper layer on said metal layer exposed by said fifth opening, followed by removing said photoresist layer, followed by removing said metal layer not under said third copper layer.

2. The method of claim 1, wherein said first polymer layer comprises polyimide.

3. The method of claim 1, wherein said metal layer comprises titanium.

4. The method of claim 1 further comprising forming a second polymer layer on said metallization structure.

5. The method of claim 4, wherein said second polymer layer comprises polyimide.

6. The method of claim 4, wherein said forming said second polymer layer comprises a spin-coating process.

7. A method for fabricating a chip, comprising:

providing a wafer comprising a silicon substrate, a transistor in or on said silicon substrate, a first copper layer over said silicon substrate, a second copper layer over said first copper layer and over said silicon substrate, a dielectric layer between said first and second copper layers, a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers, a first conductive pad over said silicon substrate, a second conductive pad over said silicon substrate, a passivation layer over said first and second copper layers and over said dielectric layer, wherein said passivation layer comprises a nitride, and wherein a first opening in said passivation layer is over said first conductive pad and exposes said first conductive pad, and a second opening in said passivation layer is over said second conductive pad and exposes said second conductive pad, wherein said first opening has a width between 0.5 and 20 micrometers, and a first polymer layer on said passivation layer, wherein a third opening in said first polymer layer is over said first conductive pad and exposes said first conductive pad, and a fourth opening in said first polymer layer is over said second conductive pad and exposes said second conductive pad, and wherein said first polymer layer has a thickness between 1 and 100 micrometers and greater than that of said passivation layer, wherein said first polymer layer is formed by a process comprising spin coating a photosensitive material, and wherein said third and fourth openings are formed by a process comprising a photolithography process; and

forming a metallization structure over said wafer, on said first polymer layer and on said first and second conductive pads, wherein said first conductive pad is connected to said second conductive pad through said metallization structure, and wherein said forming said metallization structure comprises forming a first metal layer on said first polymer layer and on said first and second conductive pads, wherein said forming said first metal layer comprises a sputtering process, followed by forming a photoresist layer on said first metal layer, wherein a fifth opening in said photoresist layer exposes said first metal layer, followed by electroplating a second metal layer on said first metal layer exposed by said fifth opening, followed by removing said photoresist layer, followed by removing said first metal layer not under said second metal layer.

8. The method of claim 7, wherein said first polymer layer comprises polyimide.

9. The method of claim 7, wherein said first metal layer comprises titanium.

10. The method of claim 7, wherein said first metal layer comprises a titanium-tungsten alloy.

11. The method of claim 7, wherein said second metal layer comprises gold.

12. The method of claim 7 further comprising forming a second polymer layer on said metallization structure.

13. The method of claim 12, wherein said second polymer layer comprises polyimide.

14. The method of claim 12, wherein said forming said second polymer layer comprises a spin-coating process.

15. A method for fabricating a chip, comprising:

providing a wafer comprising a silicon substrate, a transistor in or on said silicon substrate, a first copper layer over said silicon substrate, a second copper layer over said first copper layer and over said silicon substrate, a dielectric layer between said first and second copper layers, a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers, a conductive pad over said silicon substrate, a passivation layer over said first and second copper layers and over said dielectric layer, wherein said passivation layer comprises a nitride, and wherein a first opening in said passivation layer is over said conductive pad and exposes said conductive pad, wherein said first opening has a width between 0.5 and 20 micrometers, and a first polymer layer on said passivation layer, wherein a second opening in said first polymer layer is over said conductive pad and exposes said conductive pad, and wherein said first polymer layer has a thickness between 1 and 100 micrometers and greater than that of said passivation layer, wherein said first polymer layer is formed by a process comprising spin coating a photosensitive material, and wherein said second opening is formed by a process comprising a photolithography process; and

forming a metallization structure over said wafer, on said first polymer layer and on said conductive pad, wherein said forming said metallization structure comprises forming a metal layer on said first polymer layer and on said conductive pad, wherein said forming said metal layer comprises a sputtering process, followed by forming a photoresist layer on said metal layer, wherein a third opening in said photoresist layer exposes said metal layer, followed by electroplating a third copper layer on said metal layer exposed by said third opening, followed by removing said photoresist layer, followed by removing said metal layer not under said third copper layer.

16. The method of claim 15, wherein said first polymer layer comprises polyimide.

17. The method of claim 15, wherein said metal layer comprises titanium.

18. The method of claim 15 further comprising forming a second polymer layer on said metallization structure.

19. The method of claim 18, wherein said second polymer layer comprises polyimide.

20. The method of claim 18, wherein said forming said second polymer layer comprises a spin-coating process.