Method of manufacturing semiconductor device

• US 7,482,262 B2
• Filed: 11/14/2006
• Issued: 01/27/2009
• Est. Priority Date: 11/15/2005
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Dongbu HiTek Co., Ltd. (DB HiTek Co., Ltd.)
• Inventors: Hong, Ji Ho
• Primary Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US11/559,592
• Publication Number:
  US 20070155123A1
• Time in Patent Office: 805 Days
• Field of Search: 438/424, 438/435, 438/437, 438/624, 438/637, 438/638, 438/710, 438/711, 438/714, 438/715, 438/723, 438/724, 438/728, 438/758, 257/E21.029, 257/252, 257/257, 257/507, 257/546, 257/577, 257/579
• US Class Current: 438/624
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices

Abstract

Disclosed are embodiments relating to a method of manufacturing a semiconductor device that may improve the yield rate of the semiconductor device. In embodiments, the method may include preparing a substrate including a plurality of conductive patterns, forming first and second insulating layers on the substrate, forming a plurality of via holes by selectively etching the first and second insulating layers, forming a plurality of trenches by selectively etching the second insulating layer in such a manner that the trenches are communicated with the trenches, and forming metal interconnections in the via holes and the trenches. The width ratio of the trench to the insulating layer positioned between adjacent trenches may be in a range of 0.45 to 0.55.

Claims

1. A method comprising:

preparing a substrate including a plurality of conductive patterns;

forming an insulating layer on the substrate;

forming a plurality of trenches by selectively etching the insulating layer; and

forming a metal interconnection in each trench, wherein a width of the insulating layer positioned between adjacent trenches is in a range of approximately 0.185 μ

m to 0.225 μ

m.

2. The method of claim 1, wherein forming the trenches comprises:

forming a photoresist on the insulating layer;

selectively exposing the photoresist using a mask to form a plurality of photoresist patterns; and

etching the insulating layer using the photoresist patterns as an etch mask to form the plurality of trenches.

3. The method of claim 2, wherein a width of the photoresist pattern aligned between adjacent trenches is in a range of approximately 0.19 μ

m to 0.23 μ

m.

4. A method comprising:

preparing a substrate including a plurality of conductive patterns;

forming first and second insulating layers on the substrate;

forming a plurality of via holes by selectively etching the first and second insulating layers;

forming a plurality of trenches by selectively etching the second insulating layer such that the trenches are configured to be communicatively coupled to the via holes; and

forming metal interconnections in the trenches and via holes, wherein a width of the insulating layer positioned between adjacent trenches is in a range of approximately 0.185 μ

m to 0.225 μ

m.

5. The method of claim 4, wherein forming the via holes comprises:

forming a photoresist on the second insulating layer;

selectively exposing the photoresist using a mask to form a plurality of photoresist patterns; and

etching the first and second insulating layers using the photoresist patterns as an etch mask to form the plurality of via holes.

6. The method of claim 4, wherein forming the trenches comprises:

forming a photoresist on the second insulating layer;

selectively exposing the photoresist using a mask to form a plurality of photoresist patterns; and

etching the second insulating layer using the photoresist patterns as an etch mask to form the plurality of trenches.

7. The method of claim 6, wherein a width of the second photoresist pattern aligned between adjacent trenches is in a range of approximately 0.19 μ

m to 0.23 μ

m.

8. The method of claim 4, comprising removing a fence formed between at least one via hole and at least one trench.

9. The method of claim 8, wherein the fence is removed through an RIE (Reactive Ion Etching) process, and wherein the RIE process is performed for approximately 3 to 5 seconds using CHF₃ gas having a flow rate in a range of approximately 12 sccm to 18 sccm.

10. A method comprising:

preparing a substrate having a plurality of conductive patterns;

forming an insulating layer on the substrate;

forming a plurality of trenches by selectively etching the insulating layer; and

forming a metal interconnection in each trench, wherein a ratio of a width of the trench to a width of the insulating layer positioned between adjacent trenches is in a range of 0.45 to 0.55.

11. The method of claim 10, wherein forming the trenches comprises:

forming photoresist on the insulating layer;

selectively exposing the photoresist using a mask to form a plurality of photoresist patterns; and

etching the insulating layer using the photoresist patterns as an etch mask to form the plurality of trenches.

12. The method of claim 11, wherein a ratio of a width of a gap formed between the photoresist patterns to a width of the photoresist pattern is in a range of 0.46 to 0.56.

13. A method comprising:

preparing a substrate including a plurality of conductive patterns;

forming first and second insulating layers on the substrate;

forming a plurality of via holes by selectively etching the first and second insulating layers;

forming a plurality of trenches by selectively etching the second insulating layer such that at least one trench is configured to be in electrical communication with at least one via hole; and

forming metal interconnections in the via holes and the trenches, wherein a ratio of a width of the trench to a width of the insulating layer positioned between adjacent trenches is in a range of approximately 0.45 to 0.55.

14. The method of claim 13, wherein forming the via holes comprises:

forming a photoresist on the second insulating layer;

selectively exposing the photoresist using a mask to form a plurality of photoresist patterns; and

etching the first and second insulating layers using the photoresist patterns as an etch mask to form the plurality of via holes.

15. The method of claim 13, wherein forming the trenches comprises:

forming a photoresist on the second insulating layer;

selectively exposing the photoresist using a mask to form a plurality of photoresist patterns; and

etching the second insulating layer using the photoresist patterns as an etch mask to form a plurality of trenches.

16. The method of claim 15, wherein a ratio of a width of a gap formed between the photoresist patterns to a width of the photoresist pattern is in a range of 0.46 to 0.56.

17. The method of claim 13, further comprising removing a fence formed between at least one via hole and at least one trench.

18. The method of claim 17, wherein the fence is removed through an RIE (Reactive Ion Etching) process using CHF₃ gas.

19. The method of claim 18, wherein the RIE process is performed for 3 to 5 seconds.

20. The method of claim 18, wherein CHF₃ gas has a flow rate of between 12 sccm to 18 sccm.