Top layers of metal for integrated circuits

• US 7,482,268 B2
• Filed: 10/23/2007
• Issued: 01/27/2009
• Est. Priority Date: 09/23/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Chou, Chien-Kang, Chou, Chiu-Ming
• Primary Examiner(s): EVERHART, CARIDAD
• Application Number:
  US11/877,657
• Publication Number:
  US 20080045007A1
• Time in Patent Office: 462 Days
• Field of Search: 257/E21.314, 257/E21.627, 438/673, 438/644, 438/670, 438/739, 438/642
• US Class Current: 438/642
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 : Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 : Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 : Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.

Claims

1. A method for forming an integrated circuit chip, comprising:

providing a silicon substrate, multiple MOS devices in and on said silicon substrate, a first metallization structure over said silicon substrate, wherein said first metallization structure is connected to said multiple MOS devices, and a passivation layer over said first metallization structure, wherein a first opening in said passivation layer exposes a first contact point of said first metallization structure, and a second opening in said passivation layer exposes a second contact point of said first metallization structure; and

forming a second metallization structure on said passivation layer and over said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said second metallization structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square, and wherein said forming said second metallization structure comprises forming a titanium-containing layer, forming a first copper layer on said titanium-containing layer, forming a photoresist layer on said first copper layer, an opening in said photoresist layer exposing said first copper layer, electroplating a second copper layer on said first copper layer exposed by said opening in said photoresist layer, removing said photoresist layer, removing said first copper layer not under said second copper layer, and removing said titanium-containing layer not under said second copper layer by a wet etching process, wherein an undercut with an edge of said titanium-containing layer recessed from an edge of said second copper layer is between 0.03 and 2 micrometers.

2. The method of claim 1, wherein said forming said first copper layer comprises sputtering.

3. The method of claim 1, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers.

4. The method of claim 1, wherein said first metallization structure comprises a damascene copper and an adhesion/barrier layer under said damascene copper and at a sidewall of said damascene copper.

5. The method of claim 1 further comprising forming a polymer layer on said second metallization structure.

6. A method for forming a wirebond and a post-passivation structure for an integrated circuit chip, comprising:

providing a silicon substrate, multiple MOS devices in and on said silicon substrate, a first metallization structure over said silicon substrate, wherein said first metallization structure is connected to said multiple MOS devices, and a passivation layer over said first metallization structure, wherein a first opening in said passivation layer exposes a first contact point of said first metallization structure, and a second opening in said passivation layer exposes a second contact point of said first metallization structure; and

forming a second metallization structure on said passivation layer and over said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said second metallization structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square, and wherein said forming said second metallization structure comprises forming a titanium-containing layer, forming a seed layer on said titanium-containing layer, forming a photoresist layer on said seed layer, an opening in said photoresist layer exposing said seed layer, forming a palladium layer over said seed layer exposed by said opening in said photoresist layer, removing said photoresist layer, removing said seed layer not under said palladium layer, and removing said titanium-containing layer not under said palladium layer by a wet etching process, wherein an undercut with an edge of said titanium-containing layer recessed from an edge of said seed layer is between 0.03 and 2 micrometers; and

wirebonding to said second metallization structure.

7. The method of claim 6, wherein said forming said palladium layer comprises electroplating.

8. The method of claim 6, wherein said forming said seed layer comprises sputtering.

9. The method of claim 6, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers.

10. The method of claim 6, wherein said first metallization structure comprises a damascene copper and an adhesion/barrier layer under said damascene copper and at a sidewall of said damascene copper.

11. The method of claim 6 further comprising forming a polymer layer on said second metallization structure.

12. A method for forming a wirebond and a post-passivation structure for an integrated circuit chip, comprising:

providing a silicon substrate, multiple MOS devices in and on said silicon substrate, a first metallization structure over said silicon substrate, wherein said first metallization structure is connected to said multiple MOS devices, and a passivation layer over said first metallization structure, wherein a first opening in said passivation layer exposes a first contact point of said first metallization structure, and a second opening in said passivation layer exposes a second contact point of said first metallization structure; and

forming a second metallization structure on said passivation layer and over said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said second metallization structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square, and wherein said forming said second metallization structure comprises forming a titanium-containing layer, forming a seed layer on said titanium-containing layer, forming a photoresist layer on said seed layer, an opening in said photoresist layer exposing said seed layer, forming a gold layer over said seed layer exposed by said opening in said photoresist layer, removing said photoresist layer, removing said seed layer not under said gold layer, and removing said titanium-containing layer not under said gold layer by a wet etching process, wherein an undercut with an edge of said titanium-containing layer recessed from an edge of said seed layer is between 0.03 and 2 micrometers; and

wirebonding to said second metallization structure.

13. The method of claim 12, wherein said forming said gold layer comprises electroplating.

14. The method of claim 12, wherein said forming said seed layer comprises sputtering.

15. The method of claim 12, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers.

16. The method of claim 12, wherein said first metallization structure comprises a damascene copper and an adhesion/barrier layer under said damascene copper and at a sidewall of said damascene copper.

17. The method of claim 12 further comprising forming a polymer layer on said second metallization structure.