Multi-bit nonvolatile memory devices
First Claim
1. A multi-bit nonvolatile memory device comprising:
- a semiconductor substrate in which a recessed region is defined;
an insulating layer configured to store data within programming regions therein, the insulating layer covering a sidewall and a lower surface of the recess region;
a gate electrode on the insulating layer in the recessed region; and
at least one pair of impurity regions in the semiconductor substrate, the impurity regions adjoining a side surface of the insulating layer in the recess region and forming a relative angle that is less than 120°
therebetween with respect to a center of the gate electrode, wherein multiple different bit values are selectively stored in different programming regions of the insulating layer around the gate electrode by selective application of voltage to different ones of the impurity regions adjoining the programming regions of the insulating layer to be programmed.
1 Assignment
0 Petitions
Accused Products
Abstract
Multi-bit nonvolatile memory devices and related methods of manufacturing the same are described. In some multi-bit nonvolatile memory devices, a semiconductor substrate has a recessed region defined therein. An insulating layer, which can include an ONO layer, is configured to store data within programming regions therein, and covers a sidewall and a lower surface of the recess region. A gate electrode is on the insulating layer in the recessed region. At least one pair of impurity regions are in the semiconductor substrate. The impurity regions adjoin a side surface of the insulating layer in the recess region and form a relative angle that is less than 120° therebetween with respect to a center of the gate electrode.
-
Citations
20 Claims
-
1. A multi-bit nonvolatile memory device comprising:
-
a semiconductor substrate in which a recessed region is defined; an insulating layer configured to store data within programming regions therein, the insulating layer covering a sidewall and a lower surface of the recess region; a gate electrode on the insulating layer in the recessed region; and at least one pair of impurity regions in the semiconductor substrate, the impurity regions adjoining a side surface of the insulating layer in the recess region and forming a relative angle that is less than 120°
therebetween with respect to a center of the gate electrode, wherein multiple different bit values are selectively stored in different programming regions of the insulating layer around the gate electrode by selective application of voltage to different ones of the impurity regions adjoining the programming regions of the insulating layer to be programmed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
-
-
16. A multi-bit nonvolatile memory device comprising:
-
a semiconductor substrate in which a plurality of recess regions are defined; an insulating layer configured to store data within programming regions therein, the insulating layer covering sidewalls and lower surfaces of the plurality of recess regions; a pair of gate electrode arrays each comprising gate electrodes on the insulating layer in the plurality of recess regions, wherein the gate electrodes of a first one of the pairs of gate electrode arrays are arranged along a first line and the gate electrodes of a second one of the pairs of gate electrode arrays are arranged along a second line that is parallel to the first line; a plurality of impurity regions in the semiconductor substrate, the impurity regions arranged in the same direction as the gate electrodes of the pair of gate electrode arrays and adjoin side surfaces of the insulating layer in the recess regions; and a pair of word lines, one of the pairs of word lines is electrically connected to gate electrodes of the first one of the pairs of gate electrode arrays and is not electrically connected to gate electrodes of the second one of the pairs of gate electrode arrays, and the other one of the pairs of word lines is electrically connected to gate electrodes of the second one of the pairs of gate electrode arrays and is not electrically connected to gate electrodes of the first one of the pairs of gate electrode arrays, wherein the gate electrodes of the first one of the pairs of gate electrode arrays are spaced apart from the gate electrodes of the second one of the pairs of gate electrode arrays by a predetermined distance, and wherein multiple different bit values are selectively stored in different programming regions of the insulating layer around each of the gate electrodes by selective application of voltage to different ones of the impurity regions adjoining the programming regions of the insulating layer to be programmed. - View Dependent Claims (17, 18, 19, 20)
-
Specification