MOSgated power semiconductor device with source field electrode

• US 7,482,654 B2
• Filed: 04/20/2005
• Issued: 01/27/2009
• Est. Priority Date: 04/20/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Kent, David, Harvey, Paul, Henson, Timothy D., Thapar, Naresh, Cao, Jianjun
• Primary Examiner(s): PRENTY, MARK V
• Application Number:
  US11/110,467
• Publication Number:
  US 20060033154A1
• Time in Patent Office: 1,378 Days
• Field of Search: 257/330, 257/331, 257/339, 257/341, 257/488
• US Class Current: 257/339
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A power semiconductor device which includes a source field electrode, and at least one insulated gate electrode adjacent a respective side of the source field electrode, the source field electrode and the gate electrode being disposed in a common trench, and a method for fabricating the device.

Claims

1. A power semiconductor device comprising:

a semiconductor body having a common conduction region of one conductivity, and a base region of another conductivity, said semiconductor body including a first surface;

a trench extending from said first surface through said base region and into said common conduction region, said trench including at least two opposing sidewalls and a bottom;

a first gate insulation adjacent one of said sidewalls;

a first gate electrode adjacent said first gate insulation and spanning said base region;

a second gate insulation adjacent the other of said sidewalls;

a second gate electrode adjacent said second gate insulation and spanning said base region;

a source field electrode having a first portion and a second portion, said first portion of said source field electrode being disposed between said first and said second gate electrodes and insulated from the same by an insulation body, and said second portion of said source field electrode being disposed below said first portion and said gate electrodes;

a source region adjacent each sidewall of said trench; and

a source contact electrically connected to said source field electrode and said source regions, wherein said source field electrode extends out of said trench and above said first surface of said semiconductor body.

2. A semiconductor device according to claim 1, further comprising a first insulation cap interposed between said source contact and said first gate electrode and a second insulation cap interposed between said source contact and said second gate electrode, wherein said source field electrode is disposed between said first insulation cap and said second insulation cap.

3. A semiconductor device according to claim 1, further comprising a bottom insulation body disposed between said second portion of said source field electrode and said sidewalls and said bottom of said trench.

4. A semiconductor device according to claim 3, wherein said bottom insulation body is thicker than said gate insulations.

5. A semiconductor device according to claim 4, wherein said bottom insulation body is disposed below both gate electrodes.

6. A semiconductor device according to claim 1, wherein said source field electrode is comprised of conductive polysilicon.

7. A semiconductor device according to claim 1, wherein said gate electrodes are comprised of conductive polysilicon.

8. A semiconductor device according to claim 1, wherein said semiconductor body is comprised of epitaxial silicon.

9. A semiconductor device according to claim 8, wherein said epitaxial silicon is formed over a silicon substrate, and further comprising a drain contact ohmically connected to said silicon substrate.

10. A MOSgated power semiconductor device comprising:

an active area including at least one active cell, said active cell including at least one source region, a source contact electrode connected to said source region, a source field electrode including a first portion of a first width and a second portion of a second width, the first width being less than the second width, the source field electrode being electrically connected to said source contact, and an insulated gate electrode adjacent one side of said source field electrode and a base region, said second portion of said source field electrode extending to a depth below a depth of said insulated gate electrode and said first portion of said source field electrode extending to a height above a height of said insulated gate electrode, wherein said source field electrode and said insulated gate electrode reside within a common trench.

11. A device according to claim 10, further comprising another insulated gate electrode residing within said common trench and adjacent another side of said source field electrode and said base region.

12. A device according to claim 11, wherein each insulated gate electrode includes a respective electrode said electrode being electrically connected to one another.

13. A device according to claim 10, further comprising an insulation body adjacent a bottom portion of said source field electrode.

14. A device according to claim 10, wherein said common trench is defined in a semiconductor body and extends from a top surface of said semiconductor body to a drift region within said semiconductor body, said source field electrode extending to a height above said top surface of said semiconductor body.

15. A device according to claim 10, further comprising a termination area adjacent said active area having a termination structure, said termination structure including a termination trench adjacent said active area.

16. A device according to claim 10, wherein said insulated gate electrode includes a conductive gate electrode and further comprising a gate bus electrically connected to said gate electrode and a gate contact.

17. A device according to claim 10, further comprising a drain contact.

18. A device according to claim 10, wherein said insulated gate electrode includes an insulation cap that extends over said source region.

19. A device according to claim 11, wherein each insulated gate electrode includes a respective insulation cap, said source field electrode extending to a height above said insulation caps.