Dielectric structures having high dielectric constants, and non-volatile semiconductor memory devices having the dielectric structures

• US 7,482,677 B2
• Filed: 01/25/2006
• Issued: 01/27/2009
• Est. Priority Date: 01/25/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Jae-Hyoung, Yeo, Jae-Hyun, Lee, Jong-Cheol, Park, Young-Geun, Kim, Young-Sun, Nam, Gab-Jin, Lim, Ha-Jin, Kim, Sung-Tae, Kim, Yun-Seok, Yoo, Cha-Young
• Primary Examiner(s): Lee; Calvin
• Application Number:
  US11/339,086
• Publication Number:
  US 20060244147A1
• Time in Patent Office: 1,098 Days
• Field of Search: 257/314, 257324-325, 257/639, 257/649, 438/261, 438/287, 438785-791
• US Class Current: 257/649
• CPC Class Codes: H01L 21/02142 the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
• CPC Class Codes: H01L 21/02156 the material containing at least one rare earth element, e.g. silicate of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/31637 Deposition of Tantalum oxides, e.g. Ta2O5
• CPC Class Codes: H01L 21/31641 Deposition of Zirconium oxides, e.g. ZrO2
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Abstract

In a method of manufacturing a dielectric structure, after a tunnel oxide layer pattern is formed on a substrate, a floating gate is formed on the tunnel oxide layer. After a first dielectric layer pattern including a metal silicon oxide and a second dielectric layer pattern including a metal silicon oxynitride are formed, a control gate is formed on the dielectric structure. Since the dielectric structure includes at least one metal silicon oxide layer and at least one metal silicon oxynitride layer, the dielectric structure may have a high dielectric constant and a good thermal resistance. A non-volatile semiconductor memory device including the dielectric structure may have good electrical characteristics such as a large capacitance and a low leakage current.

Claims

1. A non-volatile semiconductor memory device comprising:

a tunnel oxide layer pattern formed on a semiconductor substrate;

a floating gate formed on the tunnel oxide layer pattern;

a dielectric structure formed on the floating gate, the dielectric structure comprising at least one first dielectric layer pattern including a metal silicon oxide and at least one second dielectric layer pattern including a metal silicon oxynitride,

wherein the at least one second dielectric layer pattern is formed on the at least one first dielectric layer pattern; and

a control gate formed on the dielectric structure.

2. The non-volatile semiconductor memory device of claim 1, wherein the floating gate comprises a first conductive layer pattern formed on the tunnel oxide layer pattern and a second conductive layer pattern formed on the first conductive layer pattern.

3. The non-volatile semiconductor memory device of claim 2, wherein the first conductive layer pattern and the second conductive layer pattern independently comprise polysilicon doped with impurities or amorphous silicon.

4. The non-volatile semiconductor memory device of claim 1, wherein the first dielectric layer pattern comprises material selected from the group consisting of a metal silicon oxide including a transition metal in Group IV, a metal silicon oxide including a transition metal in Group V and a metal silicon oxide including a rare earth metal.

5. The non-volatile semiconductor memory device of claim 4, wherein the second dielectric layer pattern comprises material selected from the group consisting of a metal silicon oxynitride including a transition metal in Group IV, a metal silicon oxynitride including a transition metal in Group V, and a metal silicon oxynitride including a rare earth metal.

6. The non-volatile semiconductor memory device of claim 1, wherein the dielectric structure comprises a plurality of first dielectric layer patterns and a plurality of second dielectric layer patterns.

7. The non-volatile semiconductor memory device of claim 1, wherein the control gate comprises doped polysilicon or polysilicon and a metal silicide.