Dielectric structures having high dielectric constants, and non-volatile semiconductor memory devices having the dielectric structures
First Claim
1. A non-volatile semiconductor memory device comprising:
- a tunnel oxide layer pattern formed on a semiconductor substrate;
a floating gate formed on the tunnel oxide layer pattern;
a dielectric structure formed on the floating gate, the dielectric structure comprising at least one first dielectric layer pattern including a metal silicon oxide and at least one second dielectric layer pattern including a metal silicon oxynitride,wherein the at least one second dielectric layer pattern is formed on the at least one first dielectric layer pattern; and
a control gate formed on the dielectric structure.
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Accused Products
Abstract
In a method of manufacturing a dielectric structure, after a tunnel oxide layer pattern is formed on a substrate, a floating gate is formed on the tunnel oxide layer. After a first dielectric layer pattern including a metal silicon oxide and a second dielectric layer pattern including a metal silicon oxynitride are formed, a control gate is formed on the dielectric structure. Since the dielectric structure includes at least one metal silicon oxide layer and at least one metal silicon oxynitride layer, the dielectric structure may have a high dielectric constant and a good thermal resistance. A non-volatile semiconductor memory device including the dielectric structure may have good electrical characteristics such as a large capacitance and a low leakage current.
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Citations
7 Claims
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1. A non-volatile semiconductor memory device comprising:
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a tunnel oxide layer pattern formed on a semiconductor substrate; a floating gate formed on the tunnel oxide layer pattern; a dielectric structure formed on the floating gate, the dielectric structure comprising at least one first dielectric layer pattern including a metal silicon oxide and at least one second dielectric layer pattern including a metal silicon oxynitride, wherein the at least one second dielectric layer pattern is formed on the at least one first dielectric layer pattern; and a control gate formed on the dielectric structure. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification