Top layers of metal for high performance IC's

• US 7,482,693 B2
• Filed: 08/21/2007
• Issued: 01/27/2009
• Est. Priority Date: 12/21/1998
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Mou-Shiung Lin
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US11/842,160
• Publication Number:
  US 20070284739A1
• Time in Patent Office: 525 Days
• Field of Search: 257750-773, 257/E23.161
• US Class Current: 257/758
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 : Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 : Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 : Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 : Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: Y10T 428/12542 : More than one such component
• CPC Class Codes: Y10T 428/12993 : Surface feature [e.g., rough, mirror]

Abstract

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Claims

1. An integrated circuit chip comprising:

a silicon substrate;

multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor in and on said silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple devices, and wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a second dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a nitride layer;

multiple power or ground pads arranged in an area array in a first region of said integrated circuit chip, wherein said area array has more than three rows and more than three columns, and wherein all pads in said area array are said multiple power or ground pads;

multiple first peripheral pads arranged along multiple edges of said integrated circuit chip;

multiple metal traces over said passivation layer;

multiple second peripheral pads arranged in more than two rings surrounding said multiple power or ground pads and in a second region surrounding said first region, wherein said multiple second peripheral pads in each of said more than two rings comprise more than ten signal pads continuously arranged, wherein one of said more than ten signal pads in one of said more than two rings is connected to one of said multiple first peripheral pads through one of said multiple metal traces, and said one of said more than ten signal pads in said one of said more than two rings has a position from a top view different from that of said one of said multiple first peripheral pads; and

multiple metal bumps on said multiple second peripheral pads.

2. The integrated circuit chip of claim 1, wherein said metallization structure comprises electroplated copper.

3. The integrated circuit chip of claim 1, wherein said multiple metal bumps comprise multiple solder bumps over said multiple second peripheral pads.

4. The integrated circuit chip of claim 1, wherein said nitride layer has a thickness between 0.5 micrometers and 2 micrometers.

5. The integrated circuit chip of claim 1, wherein said passivation layer further comprises an oxide layer under said nitride layer.

6. The integrated circuit chip of claim 1, wherein said area array has more than four rows and more than four columns.

7. The integrated circuit chip of claim 1, wherein said multiple metal traces comprise electroplated copper.

8. The integrated circuit chip of claim 1 further comprising a polymer layer on said passivation layer, wherein said multiple metal traces are further on said polymer layer.

9. The integrated circuit chip of claim 8, wherein said polymer layer has a thickness between 2 and 30 micrometers.

10. The integrated circuit chip of claim 8, wherein said polymer layer comprises polyimide.

11. An integrated circuit chip comprising:

a silicon substrate;

multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor in and on said silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple devices, and wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a second dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a nitride layer;

multiple power or ground pads arranged in an area array in a region of said integrated circuit chip, wherein said area array has more than three rows defined as multiple first rows and more than three columns, and wherein all pads in said area array are said multiple power or ground pads;

multiple first peripheral pads arranged in more than two rows defined as multiple second rows along a first edge of said integrated circuit chip, wherein said multiple first peripheral pads in each of said multiple second rows comprise more than ten signal pads continuously arranged, and wherein a first pitch between every neighboring two of said multiple first peripheral pads in each of said multiple second rows is different from a second pitch between every neighboring two of said multiple power or ground pads in each of said multiple first rows;

multiple second peripheral pads arranged in more than two rows defined as multiple third rows along a second edge of said integrated circuit chip, wherein said second edge is opposite to said first edge, wherein said multiple second peripheral pads in each of said multiple third rows comprise more than ten signal pads continuously arranged, and wherein said multiple first rows are between said multiple second rows and said multiple third rows; and

multiple metal bumps on said multiple first and second peripheral pads.

12. The integrated circuit chip of claim 11, wherein said metallization structure comprises electroplated copper.

13. The integrated circuit chip of claim 11, wherein said multiple metal bumps comprise multiple solder bumps over said multiple second peripheral pads.

14. The integrated circuit chip of claim 11, wherein said nitride layer has a thickness between 0.5 micrometers and 2 micrometers.

15. The integrated circuit chip of claim 11, wherein said passivation layer further comprises an oxide layer under said nitride layer.

16. The integrated circuit chip of claim 11, wherein said area array has more than four rows and more than four columns.

17. The integrated circuit chip of claim 11, wherein said first pitch is smaller than said second pitch.