Output buffer circuit

• US 7,482,845 B2
• Filed: 08/31/2006
• Issued: 01/27/2009
• Est. Priority Date: 10/06/2005
• Status: Expired due to Fees

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Kim, Byung Hoon, Park, Chan Woo, Choi, Won Tae, Lee, Youn Joong
• Primary Examiner(s): Luu; An T
• Application Number:
  US11/469,219
• Publication Number:
  US 20070080723A1
• Time in Patent Office: 880 Days
• Field of Search: None
• US Class Current: 327/112
• CPC Class Codes: H03F 2203/45118 At least one reactive element being added to at least one feedback circuit of a dif amp
• CPC Class Codes: H03F 2203/45248 the dif amp being designed for improving the slew rate
• CPC Class Codes: H03F 2203/45366 the AAC comprising multiple transistors parallel coupled at their gates only, e.g. in a cascode dif amp, only those forming the composite common source transistor
• CPC Class Codes: H03F 2203/45536 the FBC comprising a switch and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45626 the LC comprising biasing means controlled by the input signal
• CPC Class Codes: H03F 3/3022 CMOS common source output SEPP amplifiers H03F3/3008 takes precedence
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45219 Folded cascode stages

Abstract

Provided is an output buffer circuit having a slew rate increasing part configured with a switching element. The output buffer circuit can obtain an output voltage having a high slew rate even though a smaller amount of a bias current than that required in a conventional output buffer is used. Therefore, the output buffer circuit can reduce power consumption. In the output buffer circuit with a compensation capacitive load, an input part has two input terminal receiving differential input voltage signals, and an output part increases a gain of the differential input voltages. A current source biases the output part, and a slew rate increasing part is connected to the output part and the compensation capacitive load. The slew rate increasing part includes a switching element to increase a slew rate of the output buffer circuit.

Claims

1. An output buffer circuit with a compensation capacitive load, comprising:

an input part having two input terminal receiving differential input voltage signals;

an output part increasing a gain of the differential input voltages;

a current source biasing the output part; and

a slew rate increasing part connected to the output part and the compensation capacitive load, the slew rate increasing part including a switching element to be turned off so as to increase a slew rate of the output buffer circuit when upslewing or downslewing differential input voltages are received;

wherein the differential input voltages are settling differential input voltages; and

wherein the slew rate increasing part turns on the switching element when the settling differential input voltages are received.

2. An output buffer circuit with a compensation capacitive load, comprising:

an input part having two input terminals receiving differential input voltage signals;

an output part increasing a gain of the differential input voltages;

a floating current source biasing the output part;

a summing circuit connected to the input part and the floating current source, the summing circuit being configured to sum a current supplied from the input part and an internal current supplied from the floating current source; and

a slew rate increasing part connected to the input part and the summing circuit, the slew rate increasing part including a plurality of switching elements to increase a slew rate of the output buffer circuit.

3. The output buffer circuit according to claim 2,

wherein the differential input voltages are upslewing differential input voltages.

4. The output buffer circuit according to claim 3,

wherein the input part includes:

first and second NMOS transistors having gates receiving the upsiewing differential input voltages;

first and second PMOS transistors having gates receiving the upslewing differential input voltages;

a third NMOS transistor biasing the first and second NMOS transistors; and

a third PMOS transistor biasing the first and second PMOS transistors.

5. The output buffer circuit according to claim 3,

wherein the slew rate increasing part turns off the switching element when the upsiewing differential input voltages are received.

6. The output buffer circuit according to claim 4,

wherein the first NMOS transistor and the second PMOS transistor are turned on, and the first PMOS transistor and the second NMOS transistor are turned off.

7. The output buffer circuit according to claim 2,

wherein the differential input voltages are downslewing differential input voltages.

8. The output buffer circuit according to claim 7,

wherein the input part includes:

first and second NMOS transistors having gates receiving the downslewing differential input voltages;

first and second PMOS transistors having gates receiving the downslewing differential input voltages;

a third NMOS transistor biasing the first and second NMOS transistors; and

a third PMOS transistor biasing the first and second PMOS transistors.

9. The output buffer circuit according to claim 7,

wherein the slew rate increasing part turns off the switching element when the downslewing differential input voltages are received.

10. The output buffer circuit according to claim 8,

wherein the first PMOS transistor and the second NMOS transistor are turned on, and the first NMOS transistor and the second PMOS transistor are turned off.

11. The output buffer circuit according to claim 2,

wherein the differential input voltages are settling differential input voltages.

12. The output buffer circuit according to claim 11,

wherein the slew rate increasing part turns on the switching element when the settling differential input voltages are received.