Algorithm analog-to-digital converter
First Claim
1. An algorithm analog-to-digital converter (ADC), comprising:
- a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage;
two flash ADCs for converting one analog input signal into two digital signals n1 and n2 through different capacitor connections and outputting the two digital signals;
one multiplying digital-to-analog converter (MDAC) for amplifying a difference between an output voltage Vs of the SHA and a reference voltage ±
Vref through different capacitor connections according to the digital signals output from the flash ADCs and outputting the amplified difference to the flash ADCs again;
a sequential multiphase clock generating circuit for outputting different operating clock frequencies according to the required resolution; and
an output stage for adding the two digital signals n1 and n2 output from the flash ADCs to obtain a final output value.
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Abstract
Provided is an algorithm analog-to-digital converter (ADC). The algorithm ADC obtains two digital outputs through different capacitor connections for one analog input signal and adds the digital output signals to obtain a final output value, so that a mismatch factor of the capacitor is removed to minimize a linearity limitation resulting from the capacitor mismatch. In addition, the algorithm ADC minimizes power consumption by making the operating frequency slow at a cycle requiring a high resolution and making the operating frequency fast at a cycle requiring a low resolution, i.e., outputting different operating clock frequencies according to a required resolution.
20 Citations
13 Claims
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1. An algorithm analog-to-digital converter (ADC), comprising:
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a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage; two flash ADCs for converting one analog input signal into two digital signals n1 and n2 through different capacitor connections and outputting the two digital signals; one multiplying digital-to-analog converter (MDAC) for amplifying a difference between an output voltage Vs of the SHA and a reference voltage ±
Vref through different capacitor connections according to the digital signals output from the flash ADCs and outputting the amplified difference to the flash ADCs again;a sequential multiphase clock generating circuit for outputting different operating clock frequencies according to the required resolution; and an output stage for adding the two digital signals n1 and n2 output from the flash ADCs to obtain a final output value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification