Semiconductor memory device, and method of controlling the same
First Claim
1. A method of controlling a dynamic random access memory including dynamic memory cells, an internal voltage generator generating an internal voltage to be supplied to an internal voltage line, and a power supplying circuit supplying a power supply voltage as said internal voltage, the memory having a low power consumption mode, in which the dynamic memory cells do not retain data therein by prohibiting refresh operations, and an idle mode, comprising the steps of:
- providing a first command to the memory for entering the idle mode which operates said internal voltage generator and stops operation of said power supplying circuit; and
providing a second command to the memory during the idle mode for entering the low power consumption mode which provides said power supply voltage as said internal voltage by operating said power supplying circuit and stopping operation of said internal voltage generator.
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Accused Products
Abstract
An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
37 Citations
16 Claims
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1. A method of controlling a dynamic random access memory including dynamic memory cells, an internal voltage generator generating an internal voltage to be supplied to an internal voltage line, and a power supplying circuit supplying a power supply voltage as said internal voltage, the memory having a low power consumption mode, in which the dynamic memory cells do not retain data therein by prohibiting refresh operations, and an idle mode, comprising the steps of:
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providing a first command to the memory for entering the idle mode which operates said internal voltage generator and stops operation of said power supplying circuit; and providing a second command to the memory during the idle mode for entering the low power consumption mode which provides said power supply voltage as said internal voltage by operating said power supplying circuit and stopping operation of said internal voltage generator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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Specification