Flash card and controller with integrated voltage converter for attachment to a bus that can operate at either of two power-supply voltages

• US 7,483,329 B2
• Filed: 01/20/2007
• Issued: 01/27/2009
• Est. Priority Date: 01/06/2000
• Status: Expired due to Fees

• Current Assignee: Super Talent Electronics, Inc.
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Shen, Ming-Shiang, Luo, Jianjun, Lee, Charles C., Tsu, Chris
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US11/625,309
• Publication Number:
  US 20070147157A1
• Time in Patent Office: 738 Days
• Field of Search: 365/226, 365/227, 365/189.09
• US Class Current: 365/226
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A dual-voltage secure digital (SD) card can be inserted into a legacy host or a newer host. Legacy hosts drive a high voltage such as 3.3 volts onto the power line of the SD bus, while newer hosts drive the power line with a reduced voltage such as 1.8 volts. A flash and voltage controller chip on the SD card has a controller core that operates at the reduced voltage. A voltage regulator on the SD card, or a power management unit inside the controller chip generates an internal power voltage of 1.8 volts from the dual-voltage SD bus power line. The internal power voltage is applied to the controller core and to a voltage converter that generates a flash power voltage from the internal power voltage. The flash power voltage is applied to flash-memory chips on the SD card that operate at the higher voltage.

Claims

1. A dual-voltage protocol card comprising:

a flash-memory chip for storing blocks of data in a non-volatile flash memory;

an insertable end for inserting into a protocol socket on a host;

a bus connection formed on the insertable end, for mating with connectors on the protocol socket on the host to connect to a host protocol bus on the host;

a host power line formed on the insertable end, for connecting to a host power connector on the protocol socket;

wherein the host power line receives a high power voltage from the host socket when the host is a legacy host;

wherein the host power line receives a reduced power voltage from the host socket when the host is a reduced-voltage host, wherein the reduced power voltage is less than the high power voltage;

a voltage regulator on the dual-voltage protocol card, the voltage regulator connected to the host power line, the voltage regulator generating an internal reduced voltage from the high power voltage from the legacy host or from the reduced power voltage from the reduced-voltage host;

a controller core on the dual-voltage protocol card that receives the internal reduced voltage from the voltage regulator to power internal circuitry;

a flash controller in the controller core for communicating with the flash-memory chip;

a protocol controller in the controller core for communicating with the host;

a voltage converter that receives the internal reduced voltage from the voltage regulator, the voltage converter generating a flash power voltage from the internal reduced voltage; and

a power-supply input of the flash-memory chip that receives the flash power voltage generated by the voltage converter, wherein the flash power voltage powers the flash-memory chip,

whereby dual voltages from the legacy host or from the reduced-voltage host are converted to the internal reduced voltage to power the controller core, and to the flash power voltage to power the flash-memory chip.

2. The dual-voltage protocol card of claim 1 further comprising:

a flash and voltage controller chip that comprises the controller core and the voltage converter.

3. The dual-voltage protocol card of claim 2 wherein the voltage regulator comprises a power management unit integrated into the flash and voltage controller chip.

4. The dual-voltage protocol card of claim 2 wherein the controller core comprises:

a protocol interface for extracting host commands from host transactions received over the host protocol bus from the host;

a flash memory manager for translating addresses in the host commands to physical addresses of blocks within the flash-memory chip; and

a flash module interface for generating erase, write, and read commands of blocks in the flash-memory chip using the physical addresses from the flash memory manager.

5. The dual-voltage protocol card of claim 2 wherein the flash and voltage controller chip further comprises:

a card interface I/O connected to the host protocol bus by the bus connection, for converting I/O voltages on the host protocol bus to reduced-voltage signals to the controller core.

6. The dual-voltage protocol card of claim 5 further comprising:

a first power connection to the card interface I/O, the first power connection coupled to the host power line to receive the high power voltage from the host socket when the host is the legacy host, and to receive the reduced power voltage from the host socket when the host is the reduced-voltage host.

7. The dual-voltage protocol card of claim 2 further comprising:

a flash bus connected to the flash-memory chip, for carrying data and physical addresses of blocks being erased, written, or read in the flash-memory chip.

8. The dual-voltage protocol card of claim 7 further comprising:

a flash bus I/O connected to the flash-memory chip through the flash bus, for converting reduced-voltage signals in the controller core to I/O voltages on the flash bus.

9. The dual-voltage protocol card of claim 8 further comprising:

a second power connection to the flash bus I/O, the second power connection coupled to receive the flash power voltage from the voltage converter.

10. The dual-voltage protocol card of claim 9 wherein the flash power voltage is higher than the internal reduced voltage,

wherein the voltage converter increases the internal reduced voltage to generate the flash power voltage.

11. The dual-voltage protocol card of claim 10 wherein the voltage converter comprises a charge pump to increase voltage.

12. The dual-voltage protocol card of claim 1 wherein the high power voltage is at least 3 volts and wherein the reduced power voltage is less than 2 volts.

13. The dual-voltage protocol card of claim 12 wherein the internal reduced voltage is less than 2 volts and wherein the flash power voltage is greater than 3 volts.

14. The dual-voltage protocol card of claim 1 wherein the host protocol bus is a secure digital (SD) protocol bus having a single power line that is driven to 3.3 volts by legacy hosts and is driven to 1.8 volts by reduced-voltage hosts.

15. The dual-voltage protocol card of claim 1 wherein the host protocol bus is a secure digital (SD) protocol bus, a Multi-Media Card (MMC) protocol bus, a Compact Flash (CF) protocol bus, a Memory-Stick protocol bus, a PCI Express protocol bus, an IDE protocol bus, or a Serial ATA (SATA) protocol bus.

16. A flash-and-voltage-controller chip comprising:

a voltage regulator that generates an internal power voltage, the voltage regulator being connected to a power line to a host, the power line being driven to a high power voltage by a legacy host, the power line being driven to a reduced power voltage by a reduced-voltage host;

wherein the reduced power voltage is at least 1 volt less than the high power voltage;

a voltage converter receiving the internal power voltage from the voltage regulator, the voltage converter generating a flash power voltage that is above the internal power voltage;

a flash power output for connecting the flash power voltage generated by the voltage converter to power a flash-memory chip;

a flash bus for connecting to the flash-memory chip, the flash bus carrying address, data, and commands to the flash-memory chip;

a controller core that is powered by the internal power voltage, the controller core comprising;

a clocked-data interface to a host bus that connects to a host;

a bus transceiver for detecting and processing commands sent over the host bus;

a buffer for storing data sent over the host bus;

an internal bus coupled to the buffer;

a random-access memory (RAM) for storing instructions for execution, the RAM on the internal bus;

a central processing unit (CPU), on the internal bus, the CPU accessing and executing instructions in the RAM;

a flash-memory controller, on the internal bus, for generating flash-control signals and for buffering commands, addresses, and data to the flash bus; and

a direct-memory access (DMA) engine, on the internal bus, for transferring data over the internal bus.

17. The flash-and-voltage-controller chip of claim 16 wherein data in the flash-memory chip are accessible by the flash-memory controller sending a request sequence over the flash bus, the request sequence including a command followed by a physical address;

wherein the data in the flash-memory chip is block-addressable while the RAM is randomly-addressable by the CPU.

18. The flash-and-voltage-controller chip of claim 16 wherein the high power voltage is above 3 volts and the reduced power voltage and the internal power voltage are both below 2 volts.

19. A dual-supply-voltage flash drive comprising:

a flash-memory means for storing blocks of data in a non-volatile memory that retains data when power is lost;

a Secure Digital (SD) interface that connects to a host over a SD host bus;

a power signal in the SD interface, the power signal driven to a first power voltage by a first host, the power signal driven to a second power voltage by a second host, wherein the first power voltage and the second power voltage differ by at least one volt;

voltage regulator means, receiving the power signal from the SD interface, for generating an internal power voltage that is lower than the first power voltage;

voltage converter means, receiving the internal power voltage from the voltage regulator means, for generating a flash power voltage;

flash powering means for driving a power-supply input to the flash-memory means with the flash power voltage generated by the voltage converter means;

protocol interface means for extracting host commands from host transactions received over the SD host bus from the host;

flash memory manager means for translating addresses in the host commands to physical addresses of blocks within the flash-memory means;

flash interface means for generating erase, write, and read commands of blocks in the flash-memory means using the physical addresses from the flash memory manager means; and

internal power means, receiving the internal power voltage from the voltage regulator means, for powering the protocol interface means, the flash memory manager means, and the flash interface means with the internal power voltage.

20. The dual-supply-voltage flash drive of claim 19 wherein the protocol interface means comprises:

a SD transceiver for receiving clocked data and commands from the host bus, and for driving data onto the host bus in response to a command;

SD operating registers for storing data and commands in a format specified by a Secure Digital (SD) specification; and

a command decoder and validator, coupled to the SD operating registers, for decoding and validating a command received over the host bus by the SD transceiver.