DSP circuitry for supporting multi-channel applications by selectively shifting data through registers
First Claim
1. Digital signal processing (DSP) circuitry that independently processes a plurality of multi-channel data signals, comprising:
- a plurality of columns of registers, each said column comprising a single input, an output and a plurality of registers arranged in serial as a sequence of registers, wherein the single input is coupled to a register of the plurality of registers that is positioned first in the sequence of registers; and
interconnection circuitry for allowing a first channel of said plurality of multi-channel data signals to be selectively shifted, at the same time, through said plurality of registers in a first and a second of said columns, wherein said interconnection circuitry;
allows a value at the single input of each column to be selectively routed to any said register in said respective column by bypassing any register or registers that precede said register in said respective column, andallows the output of the first column to be selectively shifted through said plurality of registers in the second column instead of the first channel that is received by the first and second columns at the same time.
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Abstract
Digital signaling processing (DSP) circuitry that supports multiple channel or time division multiplexing (TDM) applications is provided. For example, the DSP circuitry can process one or more channels of data without mixing the data of one channel with data of another channel. DSP circuitry of the invention supports multiple channel or TDM applications by embedding a tap delay line structure within the DSP circuitry. Utilizing this embedded tap delay line structure enables the DSP circuitry to support multi-channel or TDM applications independent of any external circuitry such as logic resources, thereby freeing up those resources for other uses.
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Citations
27 Claims
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1. Digital signal processing (DSP) circuitry that independently processes a plurality of multi-channel data signals, comprising:
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a plurality of columns of registers, each said column comprising a single input, an output and a plurality of registers arranged in serial as a sequence of registers, wherein the single input is coupled to a register of the plurality of registers that is positioned first in the sequence of registers; and interconnection circuitry for allowing a first channel of said plurality of multi-channel data signals to be selectively shifted, at the same time, through said plurality of registers in a first and a second of said columns, wherein said interconnection circuitry; allows a value at the single input of each column to be selectively routed to any said register in said respective column by bypassing any register or registers that precede said register in said respective column, and allows the output of the first column to be selectively shifted through said plurality of registers in the second column instead of the first channel that is received by the first and second columns at the same time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 22, 23, 26)
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15. A programmable logic device (PLD), comprising:
digital signal processing (DSP) circuitry that supports multiple channels of data being transmitted on the same carrier, said DSP circuitry comprising; tap delay line circuitry that comprises; first and second columns of registers for selectively registering, at the same time, the same data of a first of the multiple channels such that the data of each channel is not mixed with the data of any other channel, wherein the registers are arranged in serial as a sequence of registers, a single input coupled to a register of the plurality of registers that is positioned first in the sequence of registers; and interconnection circuitry that; allows a value received at the single input to be selectively routed to any register of said registers in said tap delay line circuitry by bypassing any register or registers that precede said register in said tap delay line circuitry, and allows an output of the first column to be selectively registered in said plurality of registers in the second column instead of the data of the first channel that is received by the first and second columns at the same time; and utilization circuitry that performs a function on data received from said tap delay line circuitry. - View Dependent Claims (16, 17, 18, 19, 20, 21, 24, 25, 27)
Specification