Apparatus and method for configurable device pins

• US 7,484,027 B1
• Filed: 08/18/2005
• Issued: 01/27/2009
• Est. Priority Date: 09/20/2004
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Dahlin, Jeffrey J.
• Primary Examiner(s): Dang, Khanh
• Assistant Examiner(s): DALEY, CHRISTOPHER ANTHONY
• Application Number:
  US11/207,399
• Time in Patent Office: 1,258 Days
• Field of Search: 710/305, 710/48, 713/300
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002

Abstract

A method and apparatus for a configurable device contacts. A logic value on an external contact of a device is read. The external contact is selectively coupled to one of two voltage rails dependent upon the logic value. The logic value on the external contact is sensed to determine whether the logic value changed after selectively coupling the external contact to one of the two voltage rails. Based on the whether the external contact changed logic values, it is determined whether the external contact is coupled to receive a last address bit of an address.

Claims

1. A configurable bus interface, comprising:

a dedicated address pin to set a first address bit of a bus address;

a configurable input/output (“

I/O”

) pin configurable to alternatively operate as a data pin or an address pin; and

pin configuration logic coupled to the configurable I/O pin to determine whether the configurable I/O pin is operating to set an address bit of a bus address to identify a device for coupling to a bus via the configurable bus interface and coupled to determine whether the configurable I/O pin is alternatively operating as an I/O port for communicating with the device, the pin configuration logic is further coupled to the dedicated address pin and to the configurable I/O pin to determine if either of the dedicated address pin or the configurable I/O pin is a last address pin.

2. The configurable bus interface of claim 1, further comprising a pin controller coupled to the configurable I/O pin and to the dedicated address pin, the pin controller to selectively test the dedicated address pin and the configurable I/O pin under direction of the pin configuration logic to determine if either of the dedicated address pin or the configurable I/O pin is the last address pin.

3. The configurable bus interface of claim 2, wherein the pin controller includes:

a pull up resistor selectively coupled between a first voltage rail and the configurable I/O pin;

a pull down resistor selectively coupled between a second voltage rail and the configurable I/O pin; and

a read line coupled to the configurable I/O pin to sense a logic value on the configurable I/O pin and coupled to provide the logic value to the pin configuration logic.

4. The configurable bus interface of claim 3, wherein the pin controller further includes:

a first transistor coupled in series with the pull up resistor;

a second transistor coupled in series with the pull down resistor; and

drive logic coupled to selectively enable and disable the first and second transistors under direction of the pin configuration logic.

5. The configurable bus interface of claim 4, wherein the pin controller further comprises:

a third transistor coupled between the configurable I/O pin and the first voltage rail to selectively couple the configurable I/O pin to the first voltage rail to drive output data on the configurable I/O pin; and

a fourth transistor coupled between the configurable I/O pin and the second voltage rail to selectively couple the configurable I/O pin to the second voltage rail to drive output data on the configurable I/O pin.

6. The configurable bus interface of claim 1, further comprising:

a data bus pin to couple to the bus; and

a plurality of I/O pins to couple to the device, the configurable bus interface to interconnect the data bus to the device and to set the bus address of the device.

7. The apparatus of claim 6, further comprising:

a bus controller including the pin configuration logic, the bus controller coupled to the data bus pin, the bus controller to monitor the data bus pin and to control operation of the configurable bus interface; and

a plurality of I/O ports coupled to the plurality of I/O pins, wherein the plurality of I/O pins comprise general purpose I/O pins.

8. A method, comprising:

reading a logic value on an external contact of a device;

selectively coupling the external contact to one of two voltage rails dependent upon the logic value;

sensing whether the logic value of the external contact changes after the selectively coupling; and

determining whether the external contact is coupled to receive a last address bit of an address based on the sensing.

9. The method of claim 8, wherein the device comprises a configurable bus interface, wherein the configurable bus interface communicatively couples a bus client device to a bus, and wherein the address comprises a bus address associated with the bus client device by the configurable bus interface.

10. The method of claim 9, wherein the external contact comprises a dedicated address pin of the configurable bus interface and wherein reading the logic value comprises reading an address bit of the bus address associated with the bus client device.

11. The method of claim 9, wherein the external contact comprises a configurable input/output (“

I/O”

) pin of the configurable bus interface, the configurable I/O pin having a selectable dual purpose as an address port for receiving an address bit or an I/O port for communicating I/O data with the bus client device.

12. The method of claim 11, wherein

if the configurable I/O pin is determined to be coupled to receive the last address bit of the bus address of the bus client device, then configuring other configurable I/O pins of the configurable bus interface to communicate I/O data with the bus client device, else

if the configurable I/O pin is determined not to be coupled to receive the last address bit of the bus address of the bus client device, then configuring at least one other configurable I/O pin to receive another address bit and testing the at least one other configurable I/O pin to determine if the at least one other configurable I/O pin is coupled to receive the last address bit.

13. The method of claim 8, wherein selectively coupling the external contact to one of the two voltage rails dependent upon the logic value comprises:

internally pulling the external contact toward a HIGH voltage rail through a pull up resistor, if the logic value is a LOW logic value; and

else

internally pulling the external contact toward a LOW voltage rail through a pull down resistor, if the logic value is a HIGH logic value.

14. The method of claim 13, wherein determining whether the external contact is coupled to receive the last address bit of the address based on the sensing comprises:

determining that the external contact is not coupled to receive the last address bit of the address, if the logic value on the external contact changes due to internally pulling the external contact toward one of the two voltage rails; and

else

determining that the external contact is coupled to receive the last address bit of the address, if the logic value on the external contact remains the same after internally pulling the external contact toward one of the two voltage rails.

15. A system, comprising:

a bus;

a bus client device; and

a configurable bus interface coupling the bus client device to the bus, the configurable bus interface including;

a dedicated address contact coupled to set a first address bit of a bus address of the bus client device;

a configurable input/output (“

I/O”

) contact having a selectable dual purpose as an address port for setting an address bit of the bus address associated with the bus client device and alternatively as an I/O port for communicating I/O data with the bus client device; and

configuration logic coupled to the configurable I/O contact to determine whether the configurable I/O contact is operating to set the address bit of the bus address identifying the bus client device on the bus and to determine whether the configurable I/O pin is alternatively operating as the I/O port for communicating with the bus client device, the configuration logic is further coupled to the dedicated address contact and the dedicated address contact to determine if either of the dedicated address contact or the configurable I/O contact is a last address contact coupled to receive a last address bit of the bus address associated with the bus client device.

16. The system of claim 15, wherein the configurable bus interface further comprises a contact controller coupled to the configurable I/O contact, the contact controller coupled to test the configurable I/O contact under control of the configuration logic, the contact controller including:

a pull up resistor selectively coupled between a first voltage rail and the configurable I/O contact;

a pull down resistor selectively coupled between a second voltage rail and the configurable I/O contact; and

a read line coupled to the configurable I/O contact to sense a logic value on the configurable I/O contact and coupled to provide the logic value to the configuration logic.

17. The system of claim 15, wherein the configurable bus interface further includes:

a plurality of general purpose I/O contacts coupled to the bus client device; and

a plurality of the configurable I/O contacts, a first portion of the configurable I/O contacts each coupled to one of two voltage rails to set the bus address of the bus client device, wherein one of the first portion of configurable I/O contacts is coupled to one of the two voltage rails via a different resistance than others of the first portion indicating a last address bit, a second portion of the configurable I/O contacts coupled to the bus client device to communicate with the bus client device.

18. The system of claim 15, wherein the bus comprises an inter-integrated circuit (“

I2C”

) bus.