Semiconductor device having a mode of functional test

• US 7,484,135 B2
• Filed: 03/14/2006
• Issued: 01/27/2009
• Est. Priority Date: 07/18/2000
• Status: Expired due to Fees

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Matsui, Katsuaki
• Primary Examiner(s): Trimmings; John P
• Application Number:
  US11/374,076
• Publication Number:
  US 20060149500A1
• Time in Patent Office: 1,050 Days
• Field of Search: None
• US Class Current: 714/700
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/50012 of timing

Abstract

A semiconductor device includes a circuit block; a first signal path for guiding a test signal to a signal input terminal of the circuit block; a second signal path for guiding a test clock to a clock input terminal of the circuit block; a third signal path for guiding a test output signal from a output terminal of the circuit block to a pad via a dummy latch; and a fourth signal path for guiding the test output signal from the output terminal of the circuit block, to another pad. A dummy latch latches the test output signal at substantially a same speed as an operational latch during a normal operation. The third signal path has a wiring delay time from the output terminal to the dummy latch that is substantially equal to a wiring delay time from the output terminal to the operational latch.

Claims

1. A semiconductor device having an access time validity test mode, comprising:

a circuit block to which an input signal is input at a timing in accordance with an input clock, and which outputs an output signal having a value corresponding to said input signal;

a first signal path for guiding a test input signal, which has been supplied to a first pad, to a signal input terminal of said circuit block;

a second signal path for guiding a test clock, which has been supplied to a second pad, to a clock input terminal of said circuit block;

a third signal path for guiding a test output signal, which has been output from a signal output terminal of said circuit block, to a third pad via a dummy latch; and

a fourth signal path for guiding the test output signal, which has been output from the signal output terminal of said circuit block, to a fourth pad,

wherein the dummy latch is constituted so as to latch the test output signal at substantially a same operating speed as an operational latch for latching an output signal of said circuit block during a normal operation, and

wherein said third signal path is formed so that a wiring delay time from the signal output terminal of said circuit block to the dummy latch is substantially equal to a wiring delay time from the signal output terminal of said circuit block to the operational latch.

2. The semiconductor device according to claim 1, wherein said first signal path comprises a selector which during the normal operation supplies an output signal from a preceding circuit block to the signal input terminal of said circuit block, and which during a test operation supplies the test input signal to the signal input terminal of said circuit block.

3. The semiconductor device according to claim 1, wherein said second signal path comprises a selector which during the normal operation supplies a normal clock to the clock input terminal of said circuit block, and which during a test operation supplies the test clock to the clock input terminal of said circuit block.

4. The semiconductor device according to claim 1, wherein said third signal path comprises a selector which during the normal operation supplies a prescribed signal other than the test output signal to the third pad, and which during a test operation supplies the test output signal provided from the signal output terminal of said circuit block via the dummy latch to the third pad.

5. The semiconductor device according to claim 1, wherein said fourth signal path comprises a selector which during the normal operation supplies a prescribed signal other than the test output signal to the fourth pad, and which during a test operation supplies the test output signal to the fourth pad.

6. A semiconductor device having an access time measuring test mode, comprising:

a circuit block to which an input signal is input at a timing in accordance with an input clock, and which outputs an output signal having a value corresponding to the input signal;

an operational path for latching the output signal of said circuit block during a normal operation;

a dummy latch for latching the output signal of said circuit block during a test operation;

a first signal path for guiding a test input signal, which has been supplied to a first pad, to a signal input terminal of said circuit block;

a second signal path for guiding a test clock, which has been supplied to a second pad, to a clock input terminal of said circuit block;

a third signal path for guiding the output signal from a signal output terminal of said circuit block to an input terminal of said operational latch;

a fourth signal path for guiding the output signal from the signal output terminal of said circuit block to an input terminal of said dummy latch,

a fifth signal path for guiding a latched signal output from a signal terminal of said dummy latch to a third pad; and

a sixth signal path for guiding the output signal from the signal output terminal of said circuit block to a fourth pad,

wherein said dummy latch is constituted so that an access time from when said dummy latch has the output signal of said circuit block input thereto to when said dummy latch outputs the latched signal, is substantially equal to an access time of said operational latch, and

wherein said third and fourth signal paths are formed so that a wiring delay time from the signal output terminal of said circuit block to the input terminal of said dummy latch is substantially equal to a wiring delay time from the signal output terminal of said circuit block to the input terminal of said operational latch.

7. The semiconductor device according to claim 6, wherein said first signal path comprises a selector which during the normal operation supplies an output signal from a preceding circuit block to the signal input terminal of said circuit block, and which during the test operation supplies the test input signal to the signal input terminal of said circuit block.

8. The semiconductor device according to claim 6, wherein said second signal path comprises a selector which during the normal operation supplies a normal clock to the clock input terminal of said circuit block, and which during the test operation supplies the test clock to the clock input terminal of said circuit block.

9. The semiconductor device according to claim 6, wherein said fifth signal path comprise a selector which during the normal operation supplies a prescribed signal other than the latched signal to the third pad, and which during the test operation supplies the latched signal to the third pad.

10. The semiconductor device according to claim 6, wherein said sixth signal path comprises a selector which during the normal operation supplies a prescribed signal other than the output signal from the signal output terminal of said circuit block to the fourth pad, and which during the test operation supplies the output signal from the signal output terminal of said circuit block to the fourth pad.