Memory having variable refresh control and method therefor

• US 7,484,140 B2
• Filed: 07/07/2004
• Issued: 01/27/2009
• Est. Priority Date: 07/07/2004
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Pelley, Perry H., Burgan, John M.
• Primary Examiner(s): Trimmings; John P
• Application Number:
  US10/886,340
• Publication Number:
  US 20060010350A1
• Time in Patent Office: 1,665 Days
• Field of Search: None
• US Class Current: 714/718
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

A memory (10) has a memory array (12), a charge pump (18), a voltage regulator (20), a refresh control circuit (16), and a refresh counter (22). The charge pump (18) provides a substrate bias to the memory array (12). The voltage regulator (20) provides a pump enable signal for maintaining a voltage level of the substrate bias within upper and lower limits. The refresh control circuit (16) controls refresh operations. The refresh counter (22) is coupled to receive the pump enable signal, and in response, provides a refresh timing signal to the refresh control circuit (16) to control a refresh rate of the memory array (12). A programmable fuse circuit (26) is provided to program the refresh rate using the counter (22). The programmable fuse circuit (26) may be programmed during wafer probe testing or board level burn-in. A built-in self test (BIST) circuit (24) may be included to facilitate testing.

Claims

1. A method for testing a plurality of integrated circuit memories, each of the integrated circuit memories having a plurality of memory cells that require periodic refreshing to maintain stored data, the method comprising the steps of:

providing a semiconductor wafer having the plurality of the integrated circuit memories, each of the plurality of integrated circuit memories having a refresh counter for providing a refresh timing signal to a refresh control circuit to control a refresh rate of the plurality of memory cells;

providing a programmable fuse circuit coupled to the refresh control circuit on each of the plurality of integrated circuit memories;

providing a built-in self test (BIST) circuit on each of the plurality of integrated circuit memories for scanning test data into and out of the plurality of memory cells on each of the plurality of integrated circuit memories;

providing a plurality of wafer test pads coupled to the BIST circuits on the semiconductor wafer;

contacting the wafer test pads with wafer probe needles;

measuring a charge retention ability of the plurality of memory cells on each of the plurality of integrated circuit memories;

analyzing the charge retention ability of the plurality of memory cells on each of the plurality of integrated circuit memories to determine a plurality of refresh rates, a refresh rate corresponding to each of the plurality of integrated circuit memories; and

programming each of the programmable fuse circuits of the plurality of integrated circuit memories with its corresponding refresh rate.

2. The method of claim 1, further comprising the step of adjusting a test temperature of the semiconductor wafer.