System and method for testing a memory for a memory failure exhibited by a failing memory

• US 7,484,142 B2
• Filed: 05/11/2006
• Issued: 01/27/2009
• Est. Priority Date: 10/29/2004
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Crump, Valerie, Van Roosendaal, Brad
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US11/433,220
• Publication Number:
  US 20060218453A1
• Time in Patent Office: 992 Days
• Field of Search: 714/718, 365/201
• US Class Current: 714/718
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

A system and method for testing a memory under test on automated test equipment (ATE) that includes capturing operating conditions for a memory exhibiting a memory failure in a sequence of records corresponding the operating conditions over a period of time that includes the occurrence of the memory failure and further includes executing a software translation module to generate a file of test vectors from the sequence of records that when executed by the ATE reproduce the operating condition over the sampled period of time. The memory under test is tested according to the file of test vectors for the ATE.

Claims

1. A system for analyzing a memory system during testing operations of the memory system, comprising:

a sampling tool coupled to the memory system, the sampling tool configured to capture operating conditions of the memory system during a memory system operation and operable to generate and sequentially store a sequence of records of the sampled operating conditions for each point in time at which the operating conditions of the memory system are captured; and

a translation tool coupled to receive the sequence of records stored by the sampling tool, the translation tool operable to translate the sequence of records into a file of test vectors, the file of test vectors defining the timing and logic level of signals applied to the memory system for generating the sampled operation conditions in a memory system under test.

2. The system of claim 1 wherein the sampling tool is further operable to capture signals relative to an edge of a received clock signal.

3. The system of claim 1 wherein the translation tool comprises a computer operable to execute a translation module to translate the sequence of records.

4. The system of claim 1 wherein the test vectors further comprise test vectors that represent operating modes of the memory system.

5. The system of claim 1 further comprising automated test equipment (ATE) coupled to a memory under test and configured to receive the file of test vectors, the ATE operable to execute the file of test vectors for the memory system under test coupled to the ATE to reproduce the operating conditions of the time the signals applied to the memory system are captured, and further operable to edit the file of test vectors.

6. The system of claim 5 wherein the sampling tool captures signals applied to the memory system during which a failure of the memory system occurs, and wherein the ATE is operable to execute the file of test vectors to replicate the operating conditions which caused the memory system to fail.

7. The system of claim 6 wherein the memory system and the memory system under test each comprise a memory module having at least one of a plurality of memory devices that fails, and wherein the ATE comprises an ATE operable to parse and reorder the file of test vectors to reproduce the operating condition of the failed memory device.

8. The system of claim 5 wherein the ATE comprises an ATE operable to selectively remove test vectors from the file of test vectors during the testing of the memory system under test.

9. The system of claim 5 wherein the ATE further comprises an ATE operable to edit the file of test vectors to apply data signals representing data states that are different than the sampled data states.

10. The system of claim 5 wherein the ATE comprises an ATE operable to develop an algorithmic test program and store the algorithmic test program on an algorithmic test memory.

11. The system of claim 5 wherein the ATE comprises an ATE operable to allow a user of the ATE to edit the test vectors.

12. A system for analyzing a memory system exhibiting a memory failure, comprising:

a sampling tool coupled to the memory system, the sampling tool operable to capture a sampling of operating conditions occurring over a period of time that includes the occurrence of the memory failure, and operable to generate a sequence of records corresponding to the sampled operating conditions over the period of time;

a translation tool coupled to receive the sequence of records from the sampling tool, the translation tool operable to translate the sequence of records into a file of test patterns that corresponds to the sampled operating conditions; and

automated testing equipment (ATE) coupled to the translation tool, the ATE having a test memory in which the file of test patterns from the translation tool can be stored, the ATE operable to selectively generate test patterns and selectively remove test patterns to refine the file of test patterns stored in the test memory for testing a memory system according to the stored file of test patterns in the test memory.

13. The system of claim 12 wherein the test patterns generated by the translation tool comprises a file of test vectors.

14. The system of claim 12 wherein the sampling tool comprises a sampling tool operable to capture signals relative to an edge of a received clock signal.

15. The system of claim 12 wherein the translation tool comprises a computer operable to execute a translation module to translate the sequence of records.

16. The system of claim 12 wherein the ATE further includes an algorithmic test memory, and the ATE comprises an ATE operable to develop an algorithmic test program as part of the file of test patterns, the algorithmic test program stored in the algorithmic test memory.

17. The system of claim 12 wherein the ATE comprises an ATE operable to refine the file of test patterns to remove illegal memory operations.

18. The system of claim 12 wherein the ATE comprises an ATE operable to refine the file of test patterns to remove signal timing violations.

19. The system of claim 12 wherein the ATE comprises an ATE operable to refine the file of test patterns to add a timing margin to time specifications for the memory system.

20. The system of claim 12 wherein the ATE comprises an ATE operable to refine the file of test patterns to apply data signals representing data states that are different than the sampled data states.

21. The system of claim 12 wherein the memory system and the memory system under test each comprise a memory module having at least one of a plurality of memory devices that fails, and wherein the ATE comprises an ATE operable to parse and reorder the file of test vectors to reproduce the operating condition of the failed memory device.

22. The system of claim 12 wherein the ATE comprises an ATE operable to allow a user of the ATE to refine the file of test patterns.

23. A system for replicating operating conditions of a memory system exhibiting a failure, comprising:

a computer having a software translation module coupled to receive a sequence of records corresponding to operating conditions sampled from the memory system while exhibiting the failure, the computer configured to execute the software translation module to translate the sequence of records into a file of test vectors, the computer operable to execute the software translation module to generate as part of the file of test vectors test vectors for generating the sampled operation conditions in a memory system under test; and

a system testing tool having a test memory in which the file of test vectors can be stored, the system testing tool operable to reproduce operating conditions according to the test vectors to test the memory system under test.

24. The system of claim 23 wherein the file of test vectors comprises test vectors that represent signals captured relative to an edge of a received clock signal.

25. The system of claim 23 wherein the test vectors further comprise test vectors that represent operating modes of the memory system.

26. The system of claim 23 wherein the system testing tool includes an algorithmic test memory and the test program comprises an algorithmic test program stored in the algorithmic test memory.

27. The system of claim 26 wherein the system testing tool comprises a system testing tool operable to execute the algorithmic test program to develop a production-level test for screening the same operating conditions reproduced for the memory system under test to conducts tests on a plurality of memory systems.

28. The system of claim 23 wherein the file of test vectors includes test vectors that correspond to captured signals under which a failure of the memory system occurs, and wherein the system testing tool executes the file of test vectors to replicate the operating conditions which caused the memory system to fail.

29. The system of claim 23 wherein the system testing tool comprises a system testing tool operable to selectively remove test vectors from the file of test vectors during the testing of the memory system under test.

30. The system of claim 23 wherein the system testing tool comprises a system testing tool operable to edit the file of test vectors to remove illegal memory operations.

31. The system of claim 23 wherein the system testing tool comprises a system testing tool operable to edit the file of test vectors to remove signal timing violations.

32. The system of claim 23 wherein the system testing tool comprises a system testing tool operable to edit the file of test vectors to add a timing margin to time specifications for the memory system.

33. The system of claim 23 wherein the system testing tool comprises a system testing tool operable to edit the file of test vectors to apply data signals representing data states that are different than the sampled data states.

34. The system of claim 23 wherein the memory system and the memory system under test each comprise a memory module having at least one of a plurality of memory devices that fails, and wherein the system testing tool further comprises a system testing tool operable to parse and reorder the file of test vectors to reproduce the operating condition of the failed memory device.

35. The system of claim 23 wherein the system testing tool comprises a system testing tool operable to allow a user of the system testing tool to edit the file of test vectors.