Method of forming trench gate FETs with reduced gate to drain charge
First Claim
1. A method of forming a field effect transistor, comprising:
- forming trenches in a semiconductor region of a first conductivity type;
forming a well region of a second conductivity type in the semiconductor region;
forming source regions of the first conductivity type in the well region such that channel regions defined by a spacing between the source regions and a bottom surface of the well region are formed in the well region along opposing sidewalls of the trenches;
forming a gate dielectric layer having a non-uniform thickness along the opposing sidewalls of the trenches such that a variation in thickness of the gate dielectric layer along at least a lower portion of the channel regions is;
(i) substantially linear, and (ii) inversely dependent on a variation in doping concentration in the lower portion of the channel regions; and
forming a gate electrode in each trench.
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Abstract
A method for forming a FET includes the following steps. Trenches are formed in a semiconductor region of a first conductivity type. A well region of a second conductivity type is formed in the semiconductor region. Source regions of the first conductivity type are formed in the well region such that channel regions defined by a spacing between the source regions and a bottom surface of the well region are formed in the well region along opposing sidewalls of the trenches. A gate dielectric layer having a non-uniform thickness is formed along the opposing sidewalls of the trenches such that a variation in thickness of the gate dielectric layer along at least a lower portion of the channel regions is: (i) substantially linear, and (ii) inversely dependent on a variation in doping concentration in the lower portion of the channel regions. A gate electrode is formed in each trench.
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Citations
19 Claims
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1. A method of forming a field effect transistor, comprising:
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forming trenches in a semiconductor region of a first conductivity type; forming a well region of a second conductivity type in the semiconductor region; forming source regions of the first conductivity type in the well region such that channel regions defined by a spacing between the source regions and a bottom surface of the well region are formed in the well region along opposing sidewalls of the trenches; forming a gate dielectric layer having a non-uniform thickness along the opposing sidewalls of the trenches such that a variation in thickness of the gate dielectric layer along at least a lower portion of the channel regions is;
(i) substantially linear, and (ii) inversely dependent on a variation in doping concentration in the lower portion of the channel regions; andforming a gate electrode in each trench. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of forming a field effect transistor, comprising:
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forming trenches in a semiconductor region of a first conductivity type; forming a first insulating layer along opposing sidewalls of each trench; filling each trench with a dielectric fill material having a higher etch rate than the first insulating layer; simultaneously etching the dielectric fill material and the first insulating layer such that;
(i) an upper portion of the first insulating layer is completely removed from along an upper portion of the opposing sidewall of each trench and a remaining lower portion of the first insulating layer has a tapered edge, and (ii) a portion of the dielectric fill material remains in each trench; andforming a second insulating layer at least along upper portions of the opposing sidewalls of each trench where the first insulating layer was completely removed. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A method of forming a field effect transistor, comprising:
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forming trenches in a semiconductor region of a first conductivity type; forming a well region of a second conductivity type in the semiconductor region; forming source regions of the first conductivity type in the well region such that channel regions defined by a spacing between the source regions and a bottom surface of the well region are formed in the well region along opposing sidewalls of the trenches, and a doping concentration in the channel regions decreases from a maximum concentration in the direction from the source regions toward a bottom surface of the well region; forming a gate dielectric layer having a non-uniform thickness along the opposing sidewalls of the trenches such that a thickness of the gate dielectric layer increases in a substantially linear manner from a point below the maximum concentration in the direction from the source regions to the bottom surface of the well region; and forming a gate electrode in each trench. - View Dependent Claims (15, 16, 17, 18, 19)
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Specification