Method of making an integrated circuit
First Claim
1. A method of making an integrated circuit comprising:
- providing a substrate having a principal surface;
forming circuit devices at least one of under and on the principal surface; and
forming a stress-controlled dielectric membrane overlying the circuit devices, wherein the stress-controlled dielectric membrane is capable of forming at least one of a flexible membrane, an elastic membrane, and a free standing membrane, the stress-controlled dielectric membrane comprising one or more stress-controlled dielectric layers that are caused to have a stress of about 8×
108 dynes/cm2 or less.
1 Assignment
0 Petitions
Accused Products
Abstract
General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
258 Citations
198 Claims
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1. A method of making an integrated circuit comprising:
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providing a substrate having a principal surface; forming circuit devices at least one of under and on the principal surface; and forming a stress-controlled dielectric membrane overlying the circuit devices, wherein the stress-controlled dielectric membrane is capable of forming at least one of a flexible membrane, an elastic membrane, and a free standing membrane, the stress-controlled dielectric membrane comprising one or more stress-controlled dielectric layers that are caused to have a stress of about 8×
108 dynes/cm2 or less. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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2. The method of claim 1, wherein the one or more stress-controlled dielectric layers are caused to have a stress of 2 to 100 times less than the fracture strength of the one or more stress-controlled dielectric layers.
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3. The method of claim 2, wherein said stress is tensile.
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4. The method of claim 1, comprising forming at least one of the one stress-controlled dielectric layers by depositing one or more stress-controlled dielectric films.
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5. The method of claim 4, comprising depositing at least one of the one or more of the stress-controlled dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
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6. The method of claim 1, wherein the stress-controlled dielectric membrane is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric membrane.
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7. The method of claim 6, wherein said stress is tensile.
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8. The method of claim 1, wherein said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate.
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9. The method of claim 1, wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.
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10. The method of claim 1, wherein the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity.
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11. The method of claim 1, further comprising removing a major portion of the substrate throughout a full extent thereof without impairing the structural integrity of the integrated circuit.
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12. The method of claim 11, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
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13. The method of claim 1, further comprising:
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providing a second integrated circuit overlying the integrated circuit; and providing an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
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14. The method of claim 1, further comprising:
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providing a plurality of integrated circuits overlying the integrated circuit; and providing at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuits and the integrated circuit.
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15. The method of claim 1, wherein the one or more stress-controlled dielectric layers are caused to have a tensile stress and the integrated circuit is caused to have a thickness of about 50 microns or less.
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16. The method of claim 1, wherein the major portion of the substrate is removed prior to forming said circuitry.
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17. The method of claim 1, wherein the major portion of the substrate is removed after forming said circuitry.
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18. The method of claim 1, wherein the one or more stress-controlled dielectric layers are caused to be at least one of elastic and substantially flexible.
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19. The method of claim 1, wherein the one or more stress-controlled dielectric layers are caused to have at least one of a tensile stress and a stress of 2 to 100 times less than the fracture strength of the one or more stress-controlled dielectric layers.
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20. The method of claim 1, wherein the one or more stress-controlled dielectric layers are caused to be at least one of elastic and substantially flexible and the one or more stress-controlled dielectric layers are caused to have a tensile stress and the integrated circuit is caused to have a thickness of about 50 microns or less.
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21. The method of claim 1, further comprising forming a barrier layer in the substrate parallel to the principal surface before forming the circuit devices, the principal surface overlying the barrier layer.
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22. The method of claim 1, wherein the one or more stress-controlled dielectric layers are formed from at least one of an inorganic dielectric material and an organic dielectric material.
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23. The method of claim 22, wherein at least a major portion of the inorganic dielectric material is formed from at least one of an oxide of silicon and a nitride of silicon.
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24. The method of claim 1, further comprising a plurality of interconnect conductors formed as part of at least one of the one or more stress-controlled dielectric layers, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.
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25. The method of claim 1, further comprising at least one flexible integrated circuit overlying the integrated circuit.
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26. The method of claim 1, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
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27. The method of claim 1, wherein at least one of the one or more stress-controlled dielectric layers is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
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28. The method of claim 1, wherein at least one of the one or more stress-controlled dielectric layers is formed at a temperature of about 400°
- C.
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29. The method of claim 1, wherein at least one of said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate, the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity, the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity, the integrated circuit is caused to have a thickness of about 50 microns or less, the one or more stress-controlled dielectric layers are caused to have at least one of a tensile stress and a stress of 2 to 100 times less than the fracture strength of the one or more stress-controlled dielectric layers, at least one of the one or more stress-controlled dielectric layers is caused to be at least one of elastic and substantially flexible, at least one of the one or more stress-controlled dielectric layers is capable of forming a free standing membrane, at least one of the one or more stress-controlled dielectric layers is formed from at least one of an inorganic dielectric material and an organic dielectric material with at least a major portion of the inorganic dielectric material formed from at least one of an oxide of silicon and a nitride of silicon, at least one of the one or more stress-controlled dielectric layers is formed with at least one of electrical and optical interconnect conductors, and at least one of the one or more stress-controlled dielectric layers is deposited using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
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2. The method of claim 1, wherein the one or more stress-controlled dielectric layers are caused to have a stress of 2 to 100 times less than the fracture strength of the one or more stress-controlled dielectric layers.
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30. A method of making an integrated circuit comprising:
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providing a substrate having a principal surface; forming sources, drains, and gates of circuit devices at least one of under and on the principal surface; and forming a stress-controlled dielectric layer overlying selected ones of said sources, drains, and gates, wherein the stress-controlled dielectric layer is caused to have a stress of about 8×
108 dynes/cm2 or less, and wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane, and a free standing membrane. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53)
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31. The method of claim 30, wherein the stress-controlled dielectric layer is caused to have a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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32. The method of claim 31, wherein said stress is tensile.
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33. The method of claim 30, further comprising forming the stress-controlled dielectric layer by deposition of one or more stress-controlled dielectric films.
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34. The method of claim 33, comprising depositing at least one of the one or more of the stress-controlled dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
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35. The method of claim 30, wherein said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate.
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36. The method of claim 30, wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.
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37. The method of claim 30, wherein the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity.
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38. The method of claim 30, further comprising removing a major portion of the substrate throughout a full extent thereof without impairing the structural integrity of the integrated circuit.
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39. The method of claim 38, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
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40. The method of claim 30, wherein the stress-controlled dielectric layer is caused to have a tensile stress and the integrated circuit is caused to have a thickness of about 50 microns or less.
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41. The method of claim 30, further comprising:
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providing a second integrated circuit overlying the integrated circuit; and providing an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
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42. The method of claim 30, further comprising:
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providing a plurality of integrated circuits overlying the integrated circuit; and providing at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuits and the integrated circuit.
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43. The method of claim 30, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible.
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44. The method of claim 30, wherein the stress-controlled dielectric layer is caused to have at least one of a tensile stress and a stress of and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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45. The method of claim 30, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible and the stress-controlled dielectric layer is caused to have a tensile stress and the integrated circuit is caused to have a thickness. of about 50 micrins or less.
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46. The method of claim 30, further comprising forming a barrier layer in the substrate parallel to the principal surface before forming the circuit devices, the principal surface overlying the barrier layer.
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47. The method of claim 30, wherein the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
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48. The method of claim 47, wherein at least a major portion of the inorganic dielectric material is formed from at least one of an oxide of silicon and a nitride of silicon.
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49. The method of claim 30, further comprising a plurality of interconnect conductors formed as part of the stress-controlled dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.
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50. The method of claim 30, further comprising at least one flexible integrated circuit overlying the integrated circuit.
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51. The method of claim 30, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
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52. The method of claim 30, wherein the stress-controlled dielectric layer is formed at a temperature of about 400°
- C.
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53. The method of claim 30, wherein at least one of said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate, the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity, the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity, the integrated circuit is caused to have a thickness of about 50 microns or less, the stress-controlled dielectric layer is caused to have at least one of a tensile stress and a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer, the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible, the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material with at least a major portion of the inorganic dielectric material formed from at least one of an oxide of silicon and a nitride of silicon, the stress-controlled dielectric layer is formed with at least one of electrical and optical interconnect conductors, and the stress-controlled dielectric layer is deposited using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
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31. The method of claim 30, wherein the stress-controlled dielectric layer is caused to have a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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54. A method of making an integrated circuit comprising:
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providing a substrate having a principal surface; and forming circuitry at least one of under and on the principal surface of the substrate, said circuitry including a stress-controlled dielectric layer caused to have a stress of about 8×
108 dynes/cm2 or less, one or more electrical interconnections, and a number of active devices, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane, and a free standing membrane. - View Dependent Claims (55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77)
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55. The method of claim 54, wherein the stress-controlled dielectric layer is caused to have a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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56. The method of claim 55, wherein said stress is tensile.
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57. The method of claim 54, further comprising forming the stress-controlled dielectric layer by deposition of one or more stress-controlled dielectric films.
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58. The method of claim 57, comprising depositing at least one of the one or more of the stress-controlled dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
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59. The method of claim 54, wherein said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate.
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60. The method of claim 54, wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.
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61. The method of claim 54, wherein the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity.
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62. The method of claim 54, further comprising removing a major portion of the substrate throughout a full extent thereof without impairing the structural integrity of the integrated circuit.
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63. The method of claim 62, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
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64. The method of claim 54, further comprising:
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providing a second integrated circuit overlying the integrated circuit; and providing an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
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65. The method of claim 54, further comprising:
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providing a plurality of integrated circuits overlying the integrated circuit; and providing at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuits and the integrated circuit.
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66. The method of claim 54, wherein the stress-controlled dielectric layer is caused to have a tensile stress and the integrated circuit is caused to have a thickness of about 50 microns or less.
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67. The method of claim 54, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible.
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68. The method of claim 54, wherein the stress-controlled dielectric layer is caused to have at least one of a tensile stress and a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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69. The method of claim 54, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible and the stress-controlled dielectric layer is caused to have a tensile stress and the integrated circuit is caused to have a thickness of about 50 microns or less.
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70. The method of claim 54, further comprising forming a barrier layer in the substrate parallel to the principal surface before forming the circuitry, the principal surface overlying the barrier layer.
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71. The method of claim 54, wherein the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
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72. The method of claim 71, wherein at least a major portion of the inorganic dielectric material is formed from at least one of an oxide of silicon and a nitride of silicon.
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73. The method of claim 54, further comprising a plurality of interconnect conductors formed as part of the stress-controlled dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.
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74. The method of claim 54, further comprising at least one flexible integrated circuit overlying the integrated circuit.
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75. The method of claim 54, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
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76. The method of claim 54, wherein the stress-controlled dielectric layer is formed at a temperature of about 400°
- C.
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77. The method of claim 54, wherein at least one of said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate, the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity, the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity, the integrated circuit is caused to have a thickness of about 50 microns or less, the stress-controlled dielectric layer is caused to have at least one of a tensile stress and a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer, the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible, the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material with at least a major portion of the inorganic dielectric material formed from at least one of an oxide of silicon and a nitride of silicon, the stress-controlled dielectric layer is formed with at least one of electrical and optical interconnect conductors, and the stress-controlled dielectric layer is deposited using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
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55. The method of claim 54, wherein the stress-controlled dielectric layer is caused to have a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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78. A method of using an integrated circuit having a stress-controlled dielectric layer and interconnections formed passing through the stress-controlled dielectric layer, the method comprising:
transferring information through the stress-controlled dielectric layer by way of said interconnections, wherein the stress-controlled dielectric layer is caused to have a stress of about 8×
108 dynes/cm2 or less and is capable of forming at least one of a flexible membrane, an elastic membrane, and a free standing membrane.- View Dependent Claims (79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98)
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79. The method of claim 78, wherein the stress-controlled dielectric layer is caused to have a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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80. The method of claim 79, wherein said stress is tensile.
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81. The method of claim 78, further comprising forming the stress-controlled dielectric layer by deposition of one or more stress-controlled dielectric films.
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82. The method of claim 81, comprising depositing at least one of the one or more of the stress-controlled dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
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83. The method of claim 78, further comprising a substrate, wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.
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84. The method of claim 78, wherein the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity.
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85. The method of claim 78, further comprising a substrate and removing a major portion of the substrate throughout a full extent thereof without impairing the structural integrity of the integrated circuit.
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86. The method of claim 85, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
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87. The method of claim 78, further comprising:
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providing a second integrated circuit overlying the integrated circuit; and providing an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
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88. The method of claim 78, further comprising:
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providing a plurality of integrated circuits overlying the integrated circuit; and providing at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuits and the integrated circuit.
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89. The method of claim 78, wherein the stress-controlled dielectric layer is caused to have a tensile stress and the integrated circuit is caused to have a thickness of about 50 microns or less.
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90. The method of claim 78, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible.
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91. The method of claim 78, wherein the stress-controlled dielectric layer is caused to have at least one of a tensile stress and a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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92. The method of claim 78, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible and the stress-controlled dielectric layer is caused to have a tensile stress and the integrated circuit is caused to have a thickness of about 50 microns or less.
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93. The method of claim 78, wherein the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
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94. The method of claim 93, wherein at least a major portion of the inorganic dielectric material is formed from at least one of an oxide of silicon and a nitride of silicon.
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95. The method of claim 78, further comprising at least one flexible integrated circuit overlying the integrated circuit.
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96. The method of claim 78, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
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97. The method of claim 78, wherein the stress-controlled dielectric layer is caused to have a withstand temperature of about 400°
- C. or less.
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98. The method of claim 78, wherein at least one of the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity, the integrated circuit is caused to have a thickness of about 50 microns or less, the stress-controlled dielectric layer is caused to have at least one of a tensile stress and a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer, the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible, the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material with at least a major portion of the inorganic dielectric material formed from at least one of an oxide off silicon and a nitride of silicon, the stress-controlled dielectric layer is formed with at least one of electrical and optical interconnect conductors, and the stress-controlled dielectric layer is deposited using at least one of multiple RE energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
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79. The method of claim 78, wherein the stress-controlled dielectric layer is caused to have a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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99. A method of using an integrated circuit having a data source formed on a first portion of the integrated circuit, a data sink formed on a second portion of the integrated circuit, and interconnect circuitry connecting the data source and the data sink, a portion of the interconnect circuitry formed within a stress-controlled dielectric layer, the method comprising:
transferring data bytes between the data source and the data sink on the interconnect circuitry, wherein the stress-controlled dielectric layer is caused to have a stress of about 8×
108 dynes/cm2 or less and is capable of forming at least one of a flexible membrane, an elastic membrane, and a free standing membrane.- View Dependent Claims (100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119)
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100. The method of claim 99, wherein the stress-controlled dielectric layer is caused to have a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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101. The method of claim 100, wherein said stress is tensile.
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102. The method of claim 99, further comprising forming the stress-controlled dielectric layer by deposition of one or more stress-controlled dielectric films.
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103. The method of claim 102, comprising depositing at least one of the one or more of the stress-controlled dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
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104. The method of claim 99, further comprising a substrate, wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.
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105. The method of claim 99, wherein the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity.
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106. The method of claim 99, further comprising a substrate and removing a major portion of the substrate throughout a full extent thereof without impairing the structural integrity of the integrated circuit.
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107. The method of claim 106, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
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108. The method of claim 99, further comprising:
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a second integrated circuit overlying the integrated circuit; and interconnect connecting portions of the circuitry of the second integrated circuit and the integrated circuit.
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109. The method of claim 99, further comprising:
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providing a plurality of integrated circuits overlying the integrated circuit; and providing at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuits and the integrated circuit.
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110. The method of claim 99, wherein the stress-controlled dielectric layer are caused to have a tensile stress and the integrated circuit is caused to have a thickness of about 50 microns or less.
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111. The method of claim 99, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible.
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112. The method of claim 99, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible and the stress-controlled dielectric layer is caused to have at least one of a tensile stress and a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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113. The method of claim 99, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible and the stress-controlled dielectric layer is caused to have a tensile stress and and the integrated circuit is caused to have a thickness of about 50 microns or less.
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114. The method of claim 99, wherein the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
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115. The method of claim 114, wherein at least a major portion of the inorganic dielectric material is formed from at least one of an oxide of silicon and a nitride of silicon.
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116. The method of claim 99, further comprising at least one flexible integrated circuit overlying the integrated circuit.
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117. The method of claim 99, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
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118. The method of claim 99, wherein the stress-controlled dielectric layer is formed at a temperature of about 400°
- C.
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119. The method of claim 99, wherein at least one of the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity, the integrated circuit is caused to have a thickness of about 50 microns or less, the stress-controlled dielectric layer is caused to have at least one of a tensile stress and a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer, the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible, the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material arid an organic dielectric material with at least a major portion of the inorganic dielectric material formed from at least one of an oxide of silicon and a nitride of silicon, the stress-controlled dielectric layer is formed with at least one of electrical and optical interconnect conductors, and the stress-controlled dielectric layer is deposited using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
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100. The method of claim 99, wherein the stress-controlled dielectric layer is caused to have a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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120. A method of making an integrated circuit comprising:
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forming circuitry having active devices at least one of in and on a substrate; and forming a stress-controlled dielectric membrane wherein the stress-controlled dielectric membrane comprises one or more stress-controlled dielectric layers that are caused to have a stress of about 8×
108 dynes/cm2 or less as part of said circuitry;wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity. - View Dependent Claims (121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148)
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121. The method of claim 120, wherein the integrated circuit is able to be thinned to about 50 microns or less while retaining its structural integrity.
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122. The method of claim 120, wherein said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate.
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123. The method of claim 120, further comprising removing a major portion of the substrate.
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124. The method of claim 123, wherein the major portion of the substrate is removed prior to forming said circuitry.
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125. The method of claim 124, wherein the major portion of the substrate is removed after forming said circuitry.
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126. The method of claim 120, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
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127. The method of claim 120, wherein the stress-controlled dielectric membrane is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric membrane.
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128. The method of claim 127, wherein said stress is tensile.
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129. The method of claim 120, wherein the major portion of the substrate is removed prior to forming said circuitry.
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130. The method of claim 120, wherein the major portion of the substrate is removed after forming said circuitry.
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131. The method of claim 120, comprising forming the stress-controlled dielectric membrane by deposition of one or more stress-controlled dielectric films.
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132. The method of claim 131, comprising depositing at least one of the one or more of the stress-controlled dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
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133. The method of claim 120, further comprising:
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forming a second integrated circuit overlying the integrated circuit; and forming an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
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134. The method of claim 120, further comprising:
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forming a plurality of integrated circuits overlying the integrated circuit; and forming at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuit and the integrated circuit.
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135. The method of claim 120, wherein the one or more stress-controlled dielectric layers are caused to have a tensile stress and and the integrated circuit is caused to have a thickness of about 50 microns or less.
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136. The method of claim 120, wherein the one or more stress-controlled dielectric layers are caused to have a tensile stress and a stress of and 2 to 100 times less than the fracture strength of the one or more stress-controlled dielectric layers.
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137. The method of claim 120, wherein the one or more stress-controlled dielectric layers are caused to be at least one of elastic and substantially flexible.
-
138. The method of claim 120, wherein the one or more stress-controlled dielectric layers are caused to be one of elastic and substantially flexible and the one or more stress-controlled dielectric layers are caused to have at least one of a tensile stress and a stress of 2 to 100 times less than the fracture strength of the one or more stress-controlled dielectric layers.
-
139. The method of claim 120, wherein the one or more stress-controlled dielectric layers are caused to be one of elastic and substantially flexible and the one or more stress-controlled dielectric layers are caused to have a tensile stress and the integrated circuit is caused to have a thickness of about 50 microns or less.
-
140. The method of claim 120, further comprising:
-
providing a principal surface on the substrate; and forming a barrier layer in the substrate parallel to the principal surface before forming the circuitry having active devices, the principal surface overlying the barrier layer.
-
-
141. The method of claim 120, wherein the stress-controlled dielectric membrane is formed from at least one of an inorganic dielectric material and an organic dielectric material.
-
142. The method of claim 141, wherein at least a major portion of the inorganic dielectric material is formed from at least one of an oxide of silicon and a nitride of silicon.
-
143. The method of claim 120, further comprising a plurality of interconnect conductors formed as part of at least one of the one or more stress-controlled dielectric layers, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.
-
144. The method of claim 120, further comprising at least one flexible integrated circuit overlying the integrated circuit.
-
145. The method of claim 120, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
-
146. The method of claim 120, wherein the one or more stress-controlled dielectric layers are capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
-
147. The method of claim 120, wherein the one or more stress-controlled dielectric layers are formed at a temperature of about 400°
- C.
-
148. The method of claim 120, wherein at least one of said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate, the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity, the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity, the integrated circuit is caused to have a thickness of about 50 microns or less, the one or more stress-controlled dielectric layers are caused to have at least one of a tensile stress and a stress of 2 to 100 times less than the fracture strength of the one or more stress-controlled dielectric layers, at least one of the one or more stress-controlled dielectric layers is caused to be at least one of elastic and substantially flexible, at least one of the one or more stress-controlled dielectric layers is capable of forming a free standing membrane, at least one of the one or more stress-controlled dielectric layers is formed from at least one of an inorganic dielectric material and an organic dielectric material with at least a major portion of the inorganic dielectric material formed from at least one of an oxide of silicon and a nitride of silicon, at least one of the one or more stress-controlled dielectric layers is formed with at least one of electrical and optical interconnect conductors, and at least one of the one or more stress-controlled dielectric layers is deposited using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
-
121. The method of claim 120, wherein the integrated circuit is able to be thinned to about 50 microns or less while retaining its structural integrity.
-
-
149. A method of making an integrated circuit comprising:
-
forming circuitry having active devices at least one of in and on a substrate; and forming a stress-controlled dielectric layer that is caused to have a stress of about 8×
108 dynes/cm2 or less as part of said circuitry;wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity. - View Dependent Claims (150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174)
-
150. The method of claim 149, wherein the integrated circuit is able to be thinned to about 50 microns or less while retaining its structural integrity.
-
151. The method of claim 149, comprising forming the stress-controlled dielectric layer by deposition of one or more stress-controlled dielectric films.
-
152. The method of claim 151, comprising depositing at least one of the one or more of the stress-controlled dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
-
153. The method of claim 149, wherein said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate.
-
154. The method of claim 149, further comprising removing a major portion of the substrate.
-
155. The method of claim 154, wherein the major portion of the substrate is removed prior to forming said circuitry.
-
156. The method of claim 154, wherein the major portion of the substrate is removed after forming said circuitry.
-
157. The method of claim 149, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
-
158. The method of claim 149, wherein the stress-controlled dielectric layer is caused to have a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
-
159. The method of claim 158, wherein said stress is tensile.
-
160. The method of claim 149, further comprising:
-
forming a second integrated circuit overlying the integrated circuit; and forming an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
-
-
161. The method of claim 149, further comprising:
-
forming a plurality of integrated circuits overlying the integrated circuit; and forming at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuit and the integrated circuit.
-
-
162. The method of claim 149, wherein the stress-controlled dielectric layer is caused to have a tensile stress and the integrated circuit is caused to have a thickness of about 50 microns or less.
-
163. The method of claim 149, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible.
-
164. The method of claim 149, wherein the stress-controlled dielectric layer is caused to have at least one of a tensile stress and a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
-
165. The method of claim 149, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible and the stress-controlled dielectric layer is caused to have at least one of a tensile stress and the integrated circuit is caused to have a thickness of about 50 microns or less.
-
166. The method of claim 149, further comprising:
- providing a principal surface on the substrate; and
forming a barrier layer in the substrate parallel to the principal surface before forming the circuitry having active devices, the principal surface overlying the barrier layer.
- providing a principal surface on the substrate; and
-
167. The method of claim 149, wherein the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
-
168. The method of claim 167, wherein at least a major portion of the inorganic dielectric material is formed from at least one of an oxide of silicon and a nitride of silicon.
-
169. The method of claim 149, further comprising a plurality of interconnect conductors formed as part of the stress-controlled dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.
-
170. The method of claim 149, further comprising at least one flexible integrated circuit overlying the integrated circuit.
-
171. The method of claim 149, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
-
172. The method of claim 149, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
-
173. The method of claim 149, wherein the stress-controlled dielectric layer is formed at a temperature of about 400°
- C.
-
174. The method of claim 149, wherein at least one of the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity, the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity, the integrated circuit is caused to have a thickness of about 50 microns or less, the stress-controlled dielectric layer is caused to have at least one of a tensile stress and a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer, the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible, the stress-controlled dielectric layer is capable of forming a free standing membrane, the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material with at least a major portion of the inorganic dielectric material formed from at least one of an oxide of silicon and a nitride of silicon, the stress controlled dielectric layer is formed with at least one of electrical and optical interconnect conductors, and the stress-controlled dielectric layer is deposited using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
-
150. The method of claim 149, wherein the integrated circuit is able to be thinned to about 50 microns or less while retaining its structural integrity.
-
-
175. A method of making an integrated circuit comprising:
-
forming circuitry having active devices at least one of in and on a substrate; and forming a stress-controlled dielectric layer that is caused to have a stress of about 8×
108 dynes/cm2 or less as part of said circuitry; andremoving a major portion of the substrate throughout a full extent thereof without impairing the structural integrity of the integrated circuit. - View Dependent Claims (176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198)
-
176. The method of claim 175, wherein the major portion of the substrate is removed prior to forming said circuitry.
-
177. The method of claim 175, wherein the major portion of the substrate is removed after forming said circuitry.
-
178. The method of claim 175, comprising forming the stress-controlled dielectric layer by deposition of one or more stress-controlled dielectric films.
-
179. The method of claim 178, comprising depositing at least one of the one or more of the stress-controlled dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
-
180. The method of claim 175, wherein said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate.
-
181. The method of claim 175, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
-
182. The method of claim 175, wherein the stress-controlled dielectric layer is caused to have a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
-
183. The method of claim 182, wherein said stress is tensile.
-
184. The method of claim 175, further comprising:
-
forming a second integrated circuit overlying the integrated circuit; and forming an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
-
-
185. The method of claim 175, further comprising:
-
forming a plurality of integrated circuits overlying the integrated circuit; and forming at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuit and the integrated circuit.
-
-
186. The method of claim 175, wherein the stress-controlled dielectric layer is caused to have a tensile stress and the integrated circuit is caused to have a thickness of about 50 microns or less.
-
187. The method of claim 175, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible.
-
188. The method of claim 175, wherein the stress-controlled dielectric layer is caused to have at least one of a tensile stress and a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
-
189. The method of claim 175, wherein stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible and the stress-controlled dielectric layer is caused to have a tensile stress and the integrated circuit is caused to have a thickness of about 50 microns or less.
-
190. The method of claim 175, further comprising:
-
providing a principal surface on the substrate; and forming a barrier layer in the substrate parallel to the principal surface before forming the circuitry having active devices, the principal surface overlying the barrier layer.
-
-
191. The method of claim 175, wherein the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
-
192. The method of claim 191, wherein at least a major portion of the inorganic dielectric material is formed from at least one of an oxide of silicon and a nitride of silicon.
-
193. The method of claim 175, further comprising a plurality of interconnect conductors formed as part of the stress-controlled dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.
-
194. The method of claim 175, further comprising at least one flexible integrated circuit overlying the integrated circuit.
-
195. The method of claim 175, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
-
196. The method of claim 175, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
-
197. The method of claim 175, wherein the stress-controlled dielectric layer is formed at a temperature of about 400°
- C.
-
198. The method of claim 175, wherein at least one of the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity, the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity, the integrated circuit is caused to have a thickness of about 50 microns or less, the stress-controlled dielectric layer is caused to have at least one of a tensile stress and a stress of 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer, the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible, the stress-controlled dielectric layer is capable of forming a free standing membrane, the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material with at least a major portion of the inorganic dielectric material formed from at least one of an oxide of silicon and a nitride of silicon, the stress-controlled dielectric layer is formed with at least one of electrical and optical interconnect conductors, and the stress-controlled dielectric layer is deposited using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
-
176. The method of claim 175, wherein the major portion of the substrate is removed prior to forming said circuitry.
-
Specification
- Resources
-
Current AssigneeTaiwan Semiconductor Manufacturing Company Limited
-
Original AssigneeELM TECHNOLOGY CORPORATION
-
InventorsLeedy, Glenn J
-
Primary Examiner(s)Smith; Zandra V.
-
Assistant Examiner(s)Perkins; Pamela E
-
Application NumberUS10/665,757Publication NumberTime in Patent Office1,964 DaysField of Search438/6, 438/17, 438/53, 438/406, 438/411, 438/479, 438/626US Class Current438/626CPC Class CodesG02F 1/13452 Conductors connecting drive...G02F 1/136281 having a transmissive semic...G03F 7/70658 Electrical testingG11C 29/006 at wafer scale level, i.e. ...H01L 21/762 Dielectric regions , e.g. E...H01L 21/76264 SOI together with lateral i...H01L 21/76289 Lateral isolation by air gapH01L 21/764 Air gaps H01L21/76264 takes...H01L 21/8221 Three dimensional integrate...H01L 2224/0401 Bonding areas specifically ...H01L 2224/05552 in top viewH01L 2224/0557 the external layer being di...H01L 2224/13009 Bump connector integrally f...H01L 2224/16225 the item being non-metallic...H01L 2224/16227 the bump connector connecti...H01L 2224/80001 by connecting a bonding are...H01L 23/538 the interconnection structu...H01L 23/5381 Crossover interconnections,...H01L 23/5383 Multilayer substrates H01L2...H01L 23/5386 Geometry or layout of the i...H01L 23/5387 : Flexible insulating substra...H01L 25/0652 : the devices being arranged ...H01L 25/0655 : the devices being arranged ...H01L 25/50 : Multistep manufacturing pro...H01L 27/0207 : Geometrical layout of the c...H01L 2924/00 : Indexing scheme for arrange...H01L 2924/00011 : Not relevant to the scope o...H01L 2924/0002 : Not covered by any one of g...H01L 2924/01014 : Silicon [Si]H01L 2924/01019 : Potassium [K]H01L 2924/0102 : Calcium [Ca]H01L 2924/01057 : Lanthanum [La]H01L 2924/01078 : Platinum [Pt]H01L 2924/01079 : Gold [Au]H01L 2924/1305 : Bipolar Junction Transistor...H01L 2924/13091 : Metal-Oxide-Semiconductor F...H01L 2924/14 : Integrated circuitsH01L 2924/15153 : the die mounting substrate ...H01L 2924/15165 : Monolayer substrateH01L 2924/15312 : being a pin array, e.g. PGAH01L 2924/3011 : ImpedanceH01L 2924/3025 : Electromagnetic shieldingY10S 148/135 : Removal of substrateY10S 438/928 : Front and rear surface proc...Y10S 438/938 : Lattice strain control or u...Y10S 438/942 : MaskingY10S 438/967 : Semiconductor on specified ...Y10S 438/977 : Thinning or removal of subs...Y10T 29/49128 : Assembling formed circuit t...Y10T 29/49162 : by using wire as conductive...Y10T 29/49165 : by forming conductive walle...Y10T 29/49171 : with encapsulatingY10T 29/4921 : with bonding