Trench gate type MOS transistor semiconductor device

• US 7,485,921 B2
• Filed: 02/13/2007
• Issued: 02/03/2009
• Est. Priority Date: 02/20/2006
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamaguchi, Yoshihiro, Kawaguchi, Yusuke, Akiyama, Miwako, Ono, Syotaro
• Primary Examiner(s): Wilczewski; M.
• Assistant Examiner(s): Chiu; Tsz K
• Application Number:
  US11/674,337
• Publication Number:
  US 20070194375A1
• Time in Patent Office: 721 Days
• Field of Search: 257/288, 257/330, 257/331, 257/129, 257/139, 257/144, 257/152, 257/333, 257/341, 257/E21.384, 257/E20.021, 257/E29.201
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

This semiconductor device comprises a first semiconductor layer of a first conductivity type, an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer, and a base layer of a second conductivity type formed on the surface of the epitaxial layer. Column layers of a second conductivity type are repeatedly formed in the epitaxial layer under the base layer at a certain interval. Trenches are formed so as to penetrate the base layer to reach the epitaxial layer; and gate electrodes are formed in the trenches via a gate insulation film. A termination layer of a second conductivity type is formed on the epitaxial layer at an end region at the perimeter of the base layer. The termination layer is formed to have a junction depth larger than that of the base layer.

Claims

1. A semiconductor device comprising:

a first semiconductor layer of a first conductivity type;

an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer;

a base layer of a second conductivity type formed on the surface of the epitaxial layer;

column layers of a second conductivity type repeatedly formed in the epitaxial layer under the base layer at a certain interval;

a diffusion layer of a first conductivity type formed selectively in the base layer;

trenches formed so as to penetrate the base layer to reach the epitaxial layer;

gate electrodes formed in the trenches via a gate insulation film formed on an inner wall of the trench;

a first main electrode connected to the back side of the first semiconductor layer;

a second main electrode connected to the diffusion layer and the base layer; and

a termination layer of a second conductivity type formed on the epitaxial layer at an end region at the perimeter of the base layer, the termination layer being formed to have a junction depth larger than that of the base layer, impurity concentration of the termination layer being set lower than the impurity concentration of the column layer,

wherein the column layers are formed exclusively under the base layer.

2. The semiconductor device according to claim 1, wherein the width of the termination layer is larger than the width of the column layer.

3. The semiconductor device according to claim 1, wherein a junction depth of the termination layer is set as 40% or more of the thickness of the epitaxial layer.

4. The semiconductor device according to claim 1, further comprising second trenches formed in a surface of the base layer over the column layers.

5. The semiconductor device according to claim 4, further comprising a contact layer of a second conductivity type formed in the bottom of the second trenches.

6. The semiconductor device according to claim 1, further comprising a field plate insulation film formed over the termination layer, the second main electrode extending over the field plate insulation film.

7. The semiconductor device according to claim 1, further comprising an embedded layer of a first conductivity type with impurities concentration lower than the impurity concentration of the epitaxial layer under termination layer.

8. A semiconductor device comprising:

a first semiconductor layer of a first conductivity type;

an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer;

a base layer of a second conductivity type formed on the surface of the epitaxial layer;

column layers of a second conductivity type repeatedly formed in the epitaxial layer under the base layer at a certain interval;

a diffusion layer of a first conductivity type formed selectively in the base layer;

trenches formed so as to penetrate the base layer to reach the epitaxial layer;

gate electrodes formed in the trenches via a gate insulation film formed on an inner wall of the trench;

a first main electrode connected to the back side of the first semiconductor layer;

a second main electrode connected to the diffusion layer and the base layer; and

a semiconductor layer of a first conductivity type formed under the base layer at the perimeter of the column layer at an outermost portion and having an impurity concentration lower than the epitaxial layer.