Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
First Claim
Patent Images
1. A wafer sliced from a single crystal silicon ingot grown by the Czochralski method comprising:
- a front surface, a back surface, an imaginary central plane between the front and back surfaces, a front surface layer which comprises a first region of a wafer between the front surface and a depth, D1, measured from the front surface and toward the central plane, and a bulk layer which comprises a second region of the wafer between the central plane and the first region; and
the wafer has a resistivity of less than 5 mΩ
-cm, is doped with phosphorous or arsenic, and has a supersaturated concentration of crystal lattice vacancies in the bulk layer whereby (a) oxygen precipitates form in the bulk layer at a concentration of at least 1×
107 oxygen precipitates/cm3 upon subjecting the wafer to an oxygen precipitation heat-treatment at a temperature in excess of 700°
C., and (b) the supersaturated concentration of crystal lattice vacancies is reduced and a formation of oxygen precipitates in the bulk layer at a concentration of at least 1×
107 oxygen precipitates/cm3 is avoided by (i) heating the wafer to an annealing temperature of at least 950°
C. at a rate of at least 2°
C./sec, and (ii) cooling the wafer from the annealing temperature to 700°
C. or less before the wafer is subjected to an oxygen precipitation heat-treatment at a temperature in excess of 700°
C.
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Abstract
A process for the preparation of low resistivity arsensic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.
84 Citations
26 Claims
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1. A wafer sliced from a single crystal silicon ingot grown by the Czochralski method comprising:
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a front surface, a back surface, an imaginary central plane between the front and back surfaces, a front surface layer which comprises a first region of a wafer between the front surface and a depth, D1, measured from the front surface and toward the central plane, and a bulk layer which comprises a second region of the wafer between the central plane and the first region; and the wafer has a resistivity of less than 5 mΩ
-cm, is doped with phosphorous or arsenic, and has a supersaturated concentration of crystal lattice vacancies in the bulk layer whereby (a) oxygen precipitates form in the bulk layer at a concentration of at least 1×
107 oxygen precipitates/cm3 upon subjecting the wafer to an oxygen precipitation heat-treatment at a temperature in excess of 700°
C., and (b) the supersaturated concentration of crystal lattice vacancies is reduced and a formation of oxygen precipitates in the bulk layer at a concentration of at least 1×
107 oxygen precipitates/cm3 is avoided by (i) heating the wafer to an annealing temperature of at least 950°
C. at a rate of at least 2°
C./sec, and (ii) cooling the wafer from the annealing temperature to 700°
C. or less before the wafer is subjected to an oxygen precipitation heat-treatment at a temperature in excess of 700°
C. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Current AssigneeGlobalWafers Co., Ltd. (Sino-American Silicon Products Incorporated)
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Original AssigneeSunEdison, Inc.
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InventorsFalster, Robert J., Voronkov, Vladimir, Borionetti, Gabriella
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Primary Examiner(s)Nhu; David
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Application NumberUS11/270,790Publication NumberTime in Patent Office1,182 DaysField of Search257/347, 257/288, 257/336, 257/350, 257/401, 257/760US Class Current257/347CPC Class CodesC30B 29/06 SiliconC30B 33/02 Heat treatment C30B33/04, C...H01L 21/3225 Thermally inducing defects ...
