Method for four direction low capacitance ESD protection

• US 7,485,930 B2
• Filed: 01/12/2007
• Issued: 02/03/2009
• Est. Priority Date: 07/29/2002
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Shui-Hunyi, Lee, Jian-Hsing
• Primary Examiner(s): Pert; Evan
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US11/622,574
• Publication Number:
  US 20070108527A1
• Time in Patent Office: 753 Days
• Field of Search: 257/127, 257/173, 257/355, 257/356, 257/357, 257/358, 257/359, 257/360, 257/361, 257/362, 257/363, 257/E29.024, 257/E29.025, 257/E29.026
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0255 using diodes as protective elements

Abstract

The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

Claims

1. A low capacitance device structure with associated parasitic bipolar transistor on a substrate for the purpose of providing four-way electrostatic voltage discharge protection to a plurality of active semiconductor devices connected to an I/O logic circuit line and including ESD protection of a power bus system comprising:

isolation elements defining an active circuit area;

a first and second FET gate element upon said substrate surface;

a plurality of first, second and third doped regions of opposite dopant than said substrate, wherein said plurality of first doped regions form a source element and a drain element for said first FET gate element forming a first NFET device and said plurality of second doped regions form a source region and a drain region for said second FET gate element forming a second NFET device;

a plurality of fourth and fifth doped regions within said substrate of similar dopant as said substrate;

an electrical connection system for said first, second, third, fourth and fifth doped regions;

a surface passivation layer for said ESD protection device.

2. The structure according to claim 1 wherein said substrate consists of silicon semiconductor material doped with an acceptor element such as boron to a concentration between 1E15 and 1E16 a/cm³.

3. The structure according to claim 1 wherein said isolation elements consist of field oxide elements or shallow trench isolation elements.

4. The structure according to claim 1 wherein said plurality of first, second and third doped regions are doped with a donor element such as As to a concentration between 1E20 and 1E21 a/cm³.

5. The structure according to claim 1 wherein said plurality of fourth and fifth doped regions are doped with an acceptor element such as boron to a concentration between 1E20 and 1E21 a/cm³.

6. The structure according to claim 1 wherein said electrical connection system for said plurality of doped regions and said gate elements consists of aluminum metallurgy or aluminum doped with 1% silicon metallurgy.

7. The structure according to claim 1 wherein said source element and said first FET gate element and said source region and said second FET gate element and said plurality of fourth and fifth doped regions are connected by said electrical connector system to a second voltage source, typically ground.

8. The structure according to claim 1 wherein said first and second FET gate elements are comprised of an oxide insulator and a conductor element such as doped polysilicon.

9. The structure according to claim 1 wherein said drain element is connected by said electrical connector system to said I/O logic circuit line.

10. The structure according to claim 1 wherein said plurality of third doped regions form a N+ doped guard ring around said first NFET device.

11. The structure according to claim 10 wherein said fourth doped region forms a P+ guard ring interposed between said first NFET device and said N+ guard ring and said fifth doped region forms a P+ guard ring around said second NFET device.

12. The structure according to claim 10 wherein said drain region and said N+ guard ring are connected by said electrical connector system to a first voltage source, Vcc.