Circuits and methods for implementing sub-integer-N frequency dividers using phase rotators

• US 7,486,145 B2
• Filed: 01/10/2007
• Issued: 02/03/2009
• Est. Priority Date: 01/10/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Rylov, Sergey V., Floyd, Brian A.
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US11/621,879
• Publication Number:
  US 20080164917A1
• Time in Patent Office: 755 Days
• Field of Search: 331/1.A, 331/16, 331/74, 331/34, 377/48, 327/156, 327/115
• US Class Current: 331/1.00A
• CPC Class Codes: H03L 7/1974 for fractional frequency division

Abstract

Circuits and methods are provided for implementing programmable sub-integer N frequency dividers for use in, e.g., frequency synthesizer applications, providing glitch free outputs signals with minimal fractional spurs. Phase-rotating sub-integer N frequency dividers are programmable to provide multi-modulus division with a wide range of arbitrary sub-integer division ratios.

Claims

1. A fractional frequency divider circuit, comprising:

a prescaler circuit that divides a frequency of an input signal by a factor of A and outputs a plurality of phase-shifted signals each having a frequency of 1/A, the phase-shifted signals comprising differential I (in-phase) and Q (quadrature-phase) phase signals;

a phase rotator circuit that can phase interpolate between the plurality of phase-shifted signals output from the prescaler circuit to generate a plurality of phase-shift states having a minimum phase-shift resolution of Δ

φ

;

a phase rotator controller that generates control signals to control the operation of the phase rotator circuit, wherein the phase rotator circuit rotatably outputs one or more of the plurality of phase-shift states in accordance with an angular direction of rotation and a phase-shift output resolution, ±

k Δ

φ

, as specified by the control signals;

a postscaler circuit that divides a frequency of an output signal of the phase rotator circuit by a factor of B, and which outputs a clock signal which controls the phase rotator controller and which defines a control cycle for the phase rotator circuit;

wherein the fractional frequency divider circuit generates an arbitrary sub-integer-N divisor N(k)=(AB+Ak Δ

φ

/2π

), wherein at least k is a programmable parameter, wherein AB denotes an integer portion of the divisor, wherein where AΔ

φ

/2π

denotes a minimum fractional portion of the divisor, and wherein A and B can be integer values ≧

1.

2. The fractional frequency divider circuit of claim 1, wherein the phase rotator circuit is an M-bit phase rotator circuit that can generate a plurality of phase-shift states having a minimum phase-shift resolution

$\Delta$

⁢

⁢

ϕ

= 2 ⁢

π

2 M .

3. The fractional frequency divider circuit of claim 2, wherein k is programmable to be any integer value, including 0, where |±

k|≦

2<sup>M−

2</sup>.

4. The fractional frequency divider circuit of claim 3, wherein M=2 and k is −

1, 0, or +1 to provide a programmable tri-modulus frequency divider circuit.

5. The fractional frequency divider of claim 4, wherein A=2 and B=4 providing a programmable tri-modulus divide-by-7.5/8/8.5 frequency divider circuit.

6. The fractional frequency divider circuit of claim 3, wherein M=4 and k is −

4, −

3, −

2, −

1, 0, +1, +2, +3 or +4 to provide a programmable nine-modulus frequency divider circuit.

7. The fractional frequency divider of claim 6, wherein A=2 and B=4 providing a programmable nine-modulus divide-by-7.5/7.625/7.75/7.875/8/8.125/8.25/8.375/8.5 frequency divider circuit.

8. The fractional frequency divider of claim 1, wherein the phase rotator circuit generates a plurality of phase-shift states including I+Q, I−

Q, −

I+Q, and −

I−

Q phase-shift states by phase interpolation between the differential I and Q phase signals.

9. The fractional frequency divider of claim 1, further comprising:

a slewing buffer operatively connected between an output of the phase rotator control circuit and control signal input ports of the phase rotator, wherein the slewing buffer delays or otherwise increases a slew rate of control signals output from the phase rotator controller to smoothly interpolate from one phase-shift state to a next-phase shift state, to thereby reduce or eliminate glitches in the output signal of the phase rotator circuit; and

a limiter amplifier coupled to the output of the phase rotator to maintain a constant amplitude of the output signal of the phase rotator circuit by compensating for decreases in the amplitude of the output signal of the phase rotator which may occur by virtue of using slewed control signals.

10. A PLL (phase-locked loop) frequency synthesizer, comprising:

a phase detector;

a low pass filter coupled to the output of the phase detector;

a VCO (voltage controlled oscillator) coupled to the output of the low-pass filter;

a fractional frequency divider circuit connected in a feedback loop between an output of the VCO and an input to the phase detector, wherein the fractional frequency divider circuit comprises;

a prescaler circuit that divides a frequency of an input signal by a factor of A and outputs a plurality of phase-shifted signals each having a frequency of 1/A, the phase-shifted signals comprising differential I (in-phase) and Q (quadrature-phase) phase signals;

a phase rotator circuit that can phase interpolate between the plurality of phase-shifted signals output from the prescaler circuit to generate a plurality of phase-shift states having a minimum phase-shift resolution of Δ

φ

;

a phase rotator controller that generates control signals to control the operation of the phase rotator circuit, wherein the phase rotator circuit, rotatably outputs one or more of the plurality of phase-shift states in accordance with an angular direction of rotation and a phase-shift output resolution, ±

k Δ

φ

, as specified by the control signals;

a postscaler circuit that divides a frequency of an output signal of the phase rotator circuit by a factor of B, and which outputs a clock signal which controls the phase rotator controller and which defines a control cycle for the phase rotator circuit;

wherein the fractional frequency divider circuit generates an arbitrary sub-integer-N divisor N(k)=(AB+Ak Δ

φ

/2π

), wherein at least k is a programmable parameter, wherein AB denotes an integer portion of the divisor, wherein

$A<br><br><br><br>\frac{\mathrm{\Delta <br><br>}<br><br><br><br>\mathrm{\varphi <br><br>}}{2<br><br>\mathrm{\pi <br><br>}}$

denotes a minimum fractional portion of the divisor, and wherein A and B can be integer values ≧

1.

11. The PLL frequency synthesizer of claim 10, wherein the phase rotator circuit is an M-bit phase rotator circuit that can generate a plurality of phase-shift states having a minimum phase-shift resolution

$\mathrm{\Delta \; <li></li>}<br><br><br><br>\mathrm{\varphi <br><br>}=\frac{2<br><br>\mathrm{\pi <br><br>}}{2^M}.$

12. The PLL frequency synthesizer of claim 11, wherein k is programmable to be any integer value, including 0, where |±

k|≦

2<sup>M−

2</sup>.

13. The PLL frequency synthesizer of claim 12, wherein M=2 and k is −

1, 0, or +1 to provide a programmable tri-modulus frequency divider circuit.

14. The PLL frequency synthesizer of claim 13, wherein A=2 and B=4 providing a programmable tri-modulus divide-by-7.5/8/8.5 frequency divider circuit.

15. The PLL frequency synthesizer of claim 12, wherein M=4 and k is −

4, −

3, −

2, −

1, 0, +1, +2, +3 or +4 to provide a programmable nine-modulus frequency divider circuit.

16. The PLL frequency synthesizer of claim 15, wherein A=2 and B=4 providing a programmable nine-modulus divide-by-7.5/7.625/7.75/7.875/8/8.125/8.25/8.375/8.5 frequency divider circuit.

17. The PLL frequency synthesizer of claim 10, wherein the phase rotator circuit generates a plurality of phase-shift states including I+Q, I−

Q, −

I+Q, and −

I−

Q phase-shift states by phase interpolation between the differential I and Q phase signals.

18. The PLL frequency synthesizer of claim 10, further comprising:

a slewing buffer operatively connected between an output of the phase rotator control circuit and control signal input ports of the phase rotator, wherein the slewing buffer delays or otherwise increases a slew rate of control signals output from the phase rotator controller to smoothly interpolate from one phase-shift state to a next-phase shift state, to thereby reduce or eliminate glitches in the output signal of the phase rotator circuit; and

a limiter amplifier coupled to the output of the phase rotator to maintain a constant amplitude of the output signal of the phase rotator circuit by compensating for decreases in the amplitude of the output signal of the phase rotator which may occur by virtue of using slewed control signals.

19. A fractional frequency divider circuit, comprising:

a prescaler circuit that divides a frequency of an input signal by a factor of A and outputs a plurality of phase-shifted signals each having a frequency of 1/A, the phase-shifted signals comprising differential I (in-phase) and Q (quadrature-phase) phase signals;

a phase rotator circuit that can phase interpolate between the plurality of phase-shifted signals output from the prescaler circuit to generate a plurality of phase-shift states having a minimum phase-shift resolution of Δ

φ

;

a modulus controller that generates control signals to control the operation of the phase rotator circuit, wherein the phase rotator circuit rotatably outputs one or more of the plurality of phase-shift states in accordance with an angular direction of rotation and a phase-shift output resolution as specified by the control signals, wherein the modulus controller comprises a phase rotator control circuit and a program-swallowed framework comprising a P counter and an S counter;

a postscaler circuit that divides a frequency of an output signal of the phase rotator by a factor of B, and which outputs a clock signal which controls the modulus controller and defines a control cycle for the phase rotator circuit;

wherein the fractional frequency divider circuit generates an arbitrary sub-integer-N divisor,

$N_{\mathrm{TOT}}<br><br>\left(k_1,k_2\right)=\mathrm{ABP}+A<br><br>\frac{\mathrm{\Delta <br><br>\varphi <br><br>}}{2<br><br>\mathrm{\pi <br><br>}}<br><br>\left[{\mathrm{Pk}}_2+S<br><br>\left(k_1-k_2\right)\right],$

wherein at least k₂ and k₁ and S are programmable parameters, wherein ABP denotes an integer portion of the divisor and where

$A<br><br><br><br>\frac{\mathrm{\Delta <br><br>}<br><br><br><br>\mathrm{\varphi <br><br>}}{2<br><br>\mathrm{\pi <br><br>}}$

denotes a minimum fractional portion of the divisor, and wherein A, B and P can be integer values ≧

1, and wherein S can be an integer value ≧

0 and ≦

P.

20. The fractional frequency divider circuit of claim 19, wherein the phase rotator circuit is an M-bit phase rotator, providing a minimum phase shift resolution

$\mathrm{\Delta \; <li></li>}<br><br><br><br>\mathrm{\varphi <br><br>}=\frac{2<br><br>\mathrm{\pi <br><br>}}{2^M}.$

21. The fractional frequency divider circuit of claim 20, wherein the values of k₁ and k₂ are programmable to be any integer value, including 0, wherein |±

k₁|≦

2<sup>M−

2</sup>, |±

k₂|≦

2<sup>M−

2</sup> and k₁−

k₂=1.

22. The fractional frequency divider circuit of claim 21, wherein A=2, B=4, M=2, P=7, S is programmable from 0 to P, k₁=0, or +1 and k₂=−

1, or 0, to provide a programmable divide-by-7.5/8/8.5 tri-modulus divider with divider values from 52.5 to 59.5 in sub-integer steps of 0.5.

23. The fractional frequency divider circuit of claim 21, wherein A=2, B=4, M=2, P=8, S is programmable from 0 to P, k₁=0 or +1 and k₂=−

1 or 0, to provide a programmable divide-by-7.5/8/8.5 tri-modulus frequency divider circuit with divider values from 60.0 to 68.0 in sub-integer steps of 0.5.

24. The fractional frequency divider circuit of claim 21, wherein A=2, B=4, M=4, P=8, S is programmable from 0 to P, k₁=−

3, −

2, −

1, 0, +1, +2, +3 or +4, and k₂=−

4, −

3, −

2, −

1, 0, +1, +2, or +3, to provide a programmable divide-by-7.5/7.625/7.75/7.875/8/8.125/8.25/8.375/8.5 nine-modulus frequency divider circuit with divider values from 60.0 to 68.0 in sub-integer steps of 0.125.

25. The fractional frequency divider of claim 19, further comprising:

a slewing buffer operatively connected between an output of the phase rotator control circuit and control signal input ports of the phase rotator, wherein the slewing buffer delays or otherwise increases a slew rate of control signals output from the phase rotator controller to smoothly interpolate from one phase-shift state to a next-phase shift state, to thereby reduce or eliminate glitches in the output signal of the phase rotator circuit; and

a limiter amplifier coupled to the output of the phase rotator to maintain a constant amplitude of the output signal of the phase rotator circuit by compensating for decreases in the amplitude of the output signal of the phase rotator which may occur by virtue of using slewed control signals.

26. A PLL (phase-locked loop) frequency synthesizer, comprising:

a phase detector;

a low pass filter coupled to the output of the phase detector;

a VCO (voltage controlled oscillator) coupled to the output of the low pass filter;

a fractional frequency divider circuit connected in a feedback loop between an output of the VCO and an input to the phase-frequency detector, wherein the fractional frequency divider circuit comprises;

a prescaler circuit that divides a frequency of an input signal by a factor of A and outputs a plurality of phase-shifted signals each having a frequency 1/A, the phase-shifted signals comprising differential I (in-phase) and Q (quadrature-phase) phase signals;

a phase rotator circuit that can phase interpolate between the plurality of phase-shifted signals output from the prescaler circuit to generate a plurality of phase-shift states having a minimum phase-shift resolution of Δ

φ

;

a modulus controller that generates control signals to control the operation of the phase rotator circuit, wherein the phase rotator circuit rotatably outputs one or more of the plurality of phase-shift states in accordance with an angular direction of rotation and a phase-shift output resolution as specified by the control signals, wherein the modulus controller comprises a phase rotator control circuit and a program-swallowed framework comprising a P counter and an S counter;

a postscaler circuit that divides a frequency of an output signal of the phase rotator by a factor of B, and which outputs a clock signal which controls the modulus controller and defines a control cycle for the phase rotator circuit;

wherein the fractional frequency divider circuit generates an arbitrary sub-integer-N divisor,

$N_{\mathrm{TOT}}<br><br>\left(k_1,k_2\right)=\mathrm{ABP}+A<br><br>\frac{\mathrm{\Delta <br><br>\varphi <br><br>}}{2<br><br>\mathrm{\pi <br><br>}}<br><br>\left[{\mathrm{Pk}}_2+S<br><br>\left(k_1-k_2\right)\right],$

wherein at least k₂ and k₁ and S are programmable parameters, wherein ABP denotes an integer portion of the divisor and where

$A<br><br><br><br>\frac{\mathrm{\Delta <br><br>}<br><br><br><br>\mathrm{\varphi <br><br>}}{2<br><br>\mathrm{\pi <br><br>}}$

denotes a minimum fractional portion of the divisor, and wherein A, B and P can be integer values ≧

1, and wherein S can be an integer value ≧

0 and ≦

P.

27. The PLL frequency synthesizer circuit of claim 26, wherein the phase rotator circuit is an M-bit phase rotator, providing a minimum phase shift resolution

$\mathrm{\Delta \; \varphi <br><br>}=\frac{2<br><br>\mathrm{\pi <br><br>}}{2^M}.$

28. The PLL frequency synthesizer circuit of claim 27, wherein the values of k₁ and k₂ are programmable to be any integer value, including 0, wherein |±

k₁|≦

2<sup>M−

2</sup>, |±

k₂|≦

2<sup>M−

2</sup> and k₁−

k₂=1.

29. The PLL frequency synthesizer circuit of claim 28, wherein A=2, B=4, M=2, P=7, S is programmable from 0 to P, k₁=0, or +1 and k₂=−

1, or 0, to provide a programmable divide-by-7.5/8/8.5 tri-modulus divider with divider values from 52.5 to 59.5 in sub-integer steps of 0.5.

30. The PLL frequency synthesizer circuit of claim 28, wherein A=2, B=4, M=2, P=8, S is programmable from 0 to P, k₁=0 or +1 and k₂=−

1 or 0, to provide a programmable divide-by-7.5/8/8.5 tri-modulus frequency divider circuit with divider values from 60.0 to 68.0 in sub-integer steps of 0.5.

31. The PLL frequency synthesizer circuit of claim 28, wherein A=2, B=4, M=4, P=8, S is programmable from 0 to P, k₁=−

3, −

2, −

1, 0, +1, +2, +3 or +4 and k₂=−

4, −

3, −

2, −

1, 0, +1, +2, or +3, to provide a programmable divide-by-7.5/7.625/7.75/7.875/8/8.125/8.25/8.375/8.5 nine-modulus frequency divider circuit with divider values from 60.0 to 68.0 in sub-integer steps of 0.125.

32. The PLL frequency synthesizer of claim 26, further comprising:

a slewing buffer operatively connected between an output of the phase rotator control circuit and control signal input ports of the phase rotator, wherein the slewing buffer delays or otherwise increases a slew rate of control signals output from the phase rotator controller to smoothly interpolate from one phase-shift state to a next-phase shift state, to thereby reduce or eliminate glitches in the output signal of the phase rotator circuit; and

a limiter amplifier coupled to the output of the phase rotator to maintain a constant amplitude of the output signal of the phase rotator circuit by compensating for decreases in the amplitude of the output signal of the phase rotator which may occur by virtue of using slewed control signals.

33. A method for performing sub-integer frequency division of a frequency signal, comprising:

dividing a frequency of an input signal by a factor of A

phase interpolating between a plurality of phase-shifted signals each having, a frequency of 1/A of the input signal to generate a plurality of phase-shift states having a minimum phase-shift resolution of Δ

φ

;

rotatably outputting a phase state signal corresponding to one or more of the plurality of phase-shift states, based on control signals that specify an angular direction of rotation and a phase-shift output resolution;

dividing a frequency of an output phase state signal by a factor of B so as to achieve a sub-integer-N divisor N(k)=(AB+Ak Δ

φ

/2π

), wherein at least k is a programmable parameter, wherein AB denotes an integer portion of the divisor and where

$A<br><br><br><br>\frac{\mathrm{\Delta <br><br>}<br><br><br><br>\mathrm{\varphi <br><br>}}{2<br><br>\mathrm{\pi <br><br>}}$

denotes a minimum fractional portion of the divisor, and wherein A and B can be integer values ≧

1.