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Circuits and methods for implementing sub-integer-N frequency dividers using phase rotators

  • US 7,486,145 B2
  • Filed: 01/10/2007
  • Issued: 02/03/2009
  • Est. Priority Date: 01/10/2007
  • Status: Active Grant
First Claim
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1. A fractional frequency divider circuit, comprising:

  • a prescaler circuit that divides a frequency of an input signal by a factor of A and outputs a plurality of phase-shifted signals each having a frequency of 1/A, the phase-shifted signals comprising differential I (in-phase) and Q (quadrature-phase) phase signals;

    a phase rotator circuit that can phase interpolate between the plurality of phase-shifted signals output from the prescaler circuit to generate a plurality of phase-shift states having a minimum phase-shift resolution of Δ

    φ

    ;

    a phase rotator controller that generates control signals to control the operation of the phase rotator circuit, wherein the phase rotator circuit rotatably outputs one or more of the plurality of phase-shift states in accordance with an angular direction of rotation and a phase-shift output resolution, ±

    k Δ

    φ

    , as specified by the control signals;

    a postscaler circuit that divides a frequency of an output signal of the phase rotator circuit by a factor of B, and which outputs a clock signal which controls the phase rotator controller and which defines a control cycle for the phase rotator circuit;

    wherein the fractional frequency divider circuit generates an arbitrary sub-integer-N divisor N(k)=(AB+Ak Δ

    φ

    /2π

    ), wherein at least k is a programmable parameter, wherein AB denotes an integer portion of the divisor, wherein where AΔ

    φ

    /2π

    denotes a minimum fractional portion of the divisor, and wherein A and B can be integer values ≧

    1.

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