Shift register, scan driving circuit and display apparatus having the same

• US 7,486,269 B2
• Filed: 06/10/2004
• Issued: 02/03/2009
• Est. Priority Date: 07/09/2003
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Moon, Seung-Hwan
• Primary Examiner(s): Awad; Amr
• Assistant Examiner(s): WILLIS, RANDAL L
• Application Number:
  US10/865,216
• Publication Number:
  US 20050008114A1
• Time in Patent Office: 1,699 Days
• Field of Search: 345/98, 345/99, 345/100, 377/64, 377/72, 377/78
• US Class Current: 345/100
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A shift register includes a plurality of stages to generate a plurality of output signals, in sequence. Each of the stages includes a driving circuit, a charging circuit, a discharging circuit and a holding circuit. The driving circuit is configured to generate a first output signal in response to a first clock signal or a second clock signal having a phase different from the first clock signal. The charging circuit is configured to charge an electric charge in response to a scan start signal or a second output signal of an adjacent previous stage. The discharging circuit is configured to discharge the electric charge in response to a third output signal of an adjacent next stage. The holding circuit is configured to maintain the first output signal within a first voltage when the first output signal is in an inactive state. Therefore, a parasite capacitance is decreased to prevent a floating of a pull-up transistor.

Claims

1. A shift register having a plurality of stages to generate a plurality of output signals in sequence, each of the stages comprising:

a driving circuit configured to generate a first output signal in response to a first clock signal or a second clock signal having a phase different from the first clock signal;

a charging circuit configured to charge an electric charge in response to a scan start signal or a second output signal of an adjacent previous stage;

a discharging circuit configured to discharge the electric charge in response to a third output signal of an adjacent next stage; and

a holding circuit configured to maintain the first output signal within a first voltage when the first output signal is in an inactive state, the holding circuit comprising a first hold transistor that maintains the first output signal within the first voltage in response to the first clock signal.

2. The shift register of claim 1, wherein the holding circuit maintains the first output signal within the first voltage in response to the first or the second clock signal that is applied to the driving circuit.

3. The shift register of claim 2, wherein the holding circuit maintains the first output signal within the first voltage when the first or the second clock signal that is applied to the driving circuit is in an active state.

4. The shift register of claim 1, wherein the driving circuit comprises an output terminal via which the first output signal is outputted, and the holding circuit maintains the first output signal within the first voltage to prevent the output terminal from becoming higher than the first voltage.

5. The shift register of claim 1, wherein the driving circuit comprises a driving transistor including a first electrode that receives the first or the second clock signal that is applied to the driving circuit, and a second electrode via which the first output signal is pulled up, and the holding circuit comprises the first hold transistor including a first electrode that is electrically connected to a control electrode of the driving transistor, a second electrode that is electrically connected to the second electrode of the driving transistor and a control electrode that receives the first or the second clock signal that is applied to the driving circuit.

6. The shift register of claim 1, wherein the holding circuit further comprises a second hold transistor that includes a control electrode receiving the second clock signal, a first electrode receiving the second output signal and a second electrode electrically connected to a first electrode of the first hold transistor.

7. The shift register of claim 6, wherein the driving circuit pulls up the first output signal in response to the electric charge charged in the charging circuit and one of the first and the second clock signal applied to the driving circuit, and the driving circuit pulls down the first output signal in response to the third output signal.

8. The shift register of claim 1, further comprising a buffer that supplies the driving circuit with the scan start signal or the second output signal.

9. The shift register of claim 1, wherein the second clock signal comprises an opposite phase to the first clock signal.

10. A shift register having a plurality of stages to generate a plurality of output signals in sequence, each of the stages comprising:

a driving circuit configured to generate a first output signal in response to a first clock signal or a second clock signal having a phase different from the first clock signal;

a charging circuit configured to charge an electric charge in response to a scan start signal or a second output signal of an adjacent previous stage;

a discharging circuit configured to discharge the electric charge in response to a third output signal of an adjacent next stage;

a hold controlling circuit configured to generate a hold control signal in response to the first or the second clock signal applied to the driving circuit; and

a holding circuit configured to maintain the first output signal within a first voltage in response to the hold control signal, the holding circuit comprising a first hold transistor that maintains the first output signal within the first voltage in response to the first clock signal.

11. The shift register of claim 10, wherein the hold controlling circuit generates the hold control signal, when the first or the second clock signal applied to the driving circuit is in an active state.

12. A shift register having a plurality of stages to generate a plurality of output signals in sequence, each of the stages comprising:

a driving circuit configured to generate a first output signal in response to one of a plurality of clock signals;

a charging circuit configured to charge an electric charge in response to a scan start signal or a second output signal of an adjacent previous stage;

a discharging circuit configured to discharge the electric charge in response to a third output signal of an adjacent next stage; and

a holding circuit configured to maintain the first output signal within a first voltage when the first output signal is in an inactive state, the holding circuit comprising a first hold transistor that maintains the first output signal within the first voltage in response to the first clock signal.

13. The shift register of claim 12, wherein the holding circuit maintains the first output signal within the first voltage, when one of the plurality of clock signals applied to the driving circuit is in an active state.

14. The shift register of claim 12, wherein the holding circuit maintains the first output signal within the first voltage to prevent a floating of the driving circuit.

15. A shift register having a plurality of stages to generate a plurality of output signals in sequence, each of the stages comprising:

a charging circuit configured to charge an electric charge in response to a scan start signal or a second output signal of an adjacent previous stage;

a driving circuit configured to pull up a first output signal of a present stage in response to the electric charge and one of a first clock signal and a second clock signal having a phase different from the first clock signal, the driving circuit configured to pull down the first output signal in response to a third output signal of an adjacent next stage;

a discharging circuit configured to discharge the electric charge in response to the third output signal;

a hold controlling circuit configured to output a hold control signal in response to the first or the second clock signal applied to the driving circuit, the hold controlling circuit comprising a first hold transistor including a first electrode that receives the first clock signal, a control electrode that is electrically connected to the first electrode of the first hold transistor, and a second electrode; and

a holding circuit configured to maintain the first output signal within a first voltage in response to the hold control signal to prevent a floating of the driving circuit.

16. The shift register of claim 15, further comprising a buffer configured to supply the charging circuit with the scan start signal or the second output signal.

17. The shift register of claim 15, wherein the hold controlling circuit generates the hold control signal, when the first or the second clock signal applied to the driving circuit is in an active state.

18. The shift register of claim 15, wherein the hold controlling circuit further comprises:

a second hold transistor including a first electrode that receives the first clock signal, a control electrode that is electrically connected to the second electrode of the first hold transistor, and a second electrode that is electrically connected to the holding circuit;

a third hold transistor including a first electrode that is electrically connected to the second electrode of the first hold transistor and the control electrode of the second hold transistor, a control electrode that is electrically connected to an output terminal where the first output signal is outputted, and a second electrode receiving the first voltage; and

a fourth hold transistor including a first electrode that is electrically connected to the second electrode of the second hold transistor and the holding circuit, a control electrode that is electrically connected to the output terminal, and a second electrode receiving the first voltage.

19. The shift register of claim 15, wherein the driving circuit comprises a driving transistor including a first electrode that receives the first clock signal and a second electrode, via which the first output signal is pulled up, and the holding circuit comprises a fifth hold transistor including a control electrode that receives the first clock signal via the hold controlling circuit, a first electrode that is electrically connected to the second electrode of the driving transistor, and a second electrode that receives the first voltage.

20. The shift register of claim 19, wherein the fifth hold transistor is turned on to maintain the second electrode of the driving transistor within the first voltage, when the first clock signal is in an active state and the first output signal is an inactive state.

21. The shift register of claim 19, wherein the holding circuit further comprises a sixth hold transistor including a control electrode that receives the second clock signal, a first electrode that is electrically connected to the second electrode of the driving transistor, and a second electrode that receives the first voltage.

22. The shift register of claim 21, wherein the fifth hold transistor is turned on to maintain the second electrode of the driving transistor within the first voltage, when the first clock signal is in an active state and the first output signal is an inactive state.

23. The shift register of claim 21, wherein the sixth hold transistor is turned on to maintain the second electrode of the driving transistor within the first voltage, when the second clock signal is in an active state and the first output signal is an inactive state.

24. A scan driving circuit including a plurality of stages to generate a plurality of output signals in sequence, each of the stages comprising:

a charging circuit configured to charge an electric charge in response to a scan start signal or a second output signal of an adjacent previous stage;

a driving circuit configured to pull up a first output signal of a present stage in response to the electric charge and one of a first clock signal and a second clock signal having a phase different from the first clock signal, the driving circuit configured to pull down the first output signal in response to a third output signal of an adjacent next stage;

a discharging circuit configured to discharge the electric charge in response to the third output signal; and

a holding circuit configured to maintain the first output signal within a first voltage in response to the first or the second clock signal applied to the driving circuit to prevent a floating of the driving circuit, the holding circuit comprising a first hold transistor including a first electrode that is electrically connected to the control electrode of the driving transistor, a second electrode that is electrically connected to the second electrode of the driving transistor, and a control electrode receiving the first clock signal.

25. The scan driving circuit of claim 24, further comprising a buffer configured to supply the charging circuit with the scan start signal or the second output signal.

26. The scan driving circuit of claim 24, wherein the driving circuit comprises a driving transistor including a first electrode that receives the first clock signal, a control electrode and a second electrode, via which the first output signal is pulled up, and the holding circuit comprises a first hold transistor including a first electrode electrically connected to the control electrode of the driving transistor, a second electrode electrically connected to the second electrode of the driving transistor and a control electrode receiving the first clock signal.

27. The scan driving circuit of claim 24, wherein the driving circuit comprises a driving transistor including a first electrode that receives the first clock signal to pull up the first output signal of the present stage via a second electrode of the driving circuit,

and wherein the holding circuit further comprises a second hold transistor including a control electrode that receives the second clock signal, a first electrode that receives the second output signal, and a second electrode that is electrically connected to the first electrode of the first hold transistor.

28. The scan driving circuit of claim 24, wherein the stage further comprises a hold controlling circuit that controls the holding circuit, when the first clock signal is in an active state.

29. The scan driving circuit of claim 28, wherein the hold controlling circuit comprises:

a first hold transistor including a first electrode that receives the first clock signal and a control electrode that is electrically connected to the first electrode thereof;

a second hold transistor including a first electrode that receives the first clock signal, a control electrode that is electrically connected to the second electrode of the first hold transistor, and a second electrode that is electrically connected to the holding circuit;

a third hold transistor including a first electrode that is electrically connected to the second electrode of the first hold transistor and the control electrode of the second hold transistor, a control electrode that is electrically connected to an output terminal where the first output signal is outputted, and a second electrode receiving the first voltage; and

a fourth hold transistor including a first electrode that is electrically connected to the second electrode of the second hold transistor and the holding circuit, a control electrode that is electrically connected to the output terminal, and a second electrode receiving the first voltage.

30. The scan driving circuit of claim 28, wherein the driving circuit comprises a driving transistor including a first electrode that receives the first clock signal and a second electrode, via which the first output signal is pulled up, and the holding circuit comprises a fifth hold transistor including a control electrode that receives the first clock signal via the hold controlling circuit, a first electrode that is electrically connected to the second electrode of the driving transistor, and a second electrode that receives the first voltage.

31. The scan driving circuit of claim 30, wherein the holding circuit further comprises a sixth hold transistor including a control electrode that receives the second clock signal, a first electrode that is electrically connected to the second electrode of the driving transistor, and a second electrode that receives the first voltage.

32. A display apparatus including a display cell array circuit that is disposed on a substrate to have a plurality of data lines and a plurality of scan lines and a shift register that includes a plurality of stages to generate a plurality of output signals in sequence, each of the stages comprising:

a driving circuit configured to generate a first output signal of a present stage in response to a first clock signal or a second clock signal having a phase different from the first clock signal;

a charging circuit configured to charge an electric charge in response to the scan start signal or the second output signal;

a discharging circuit configured to discharge the electric charge charged in the charging circuit in response to a third output signal of an adjacent next stage; and

a holding circuit configured to maintain the first output signal of the present stage within a first voltage, the holding circuit comprising a first hold transistor that maintains the first output signal within the first voltage in response to the first clock signal.

33. The display apparatus of claim 32, wherein the stage further comprises a hold controlling circuit that controls the holding circuit, when the first clock signal is in an active state.

34. The display apparatus of claim 32, wherein the holding circuit maintains the first output signal of the present stage within the first voltage, when the first or the second clock signal applied to the driving circuit is in an active state.

35. The display apparatus of claim 32, wherein the holding circuit maintains the first output signal within the first voltage to prevent a floating of the driving circuit.

36. A display apparatus comprising:

a display cell array circuit disposed on a substrate to include a plurality of data lines and a plurality of scan lines;

a first scan driving circuit including a shift register that has a plurality of stages to generate a plurality of output signals corresponding to the stages to the scan lines in sequence, a first stage receiving a scan staff signal, each of the output terminals being electrically connected to each of first ends of the scan lines; and

a second scan driving circuit electrically connected to second ends of the scan lines to discharge electric charges formed by the output signals that are applied to the scan lines, the second scan driving circuit including a first hold transistor comprising;

a first electrode electrically connected to a second end of the scan lines which corresponds to a present stage;

a second electrode which receives a second voltage; and

a control electrode electrically connected to a second end of the scan lines which corresponds to an adjacent next stage.

37. The display apparatus of claim 36, wherein each of the stages comprises:

a driving circuit configured to generate a first output signal in response to a first clock signal or a second clock signal having a phase different from the first clock signal;

a charging circuit configured to charge an electric charge in response to a scan start signal or a second output signal of an adjacent previous stage;

a discharging circuit configured to discharge the electric charge in response to a third output signal of the adjacent next stage; and

a holding circuit configured to maintain the first output signal within a first voltage.

38. The display apparatus of claim 37, wherein each of the stages further comprises a buffer configured to supply the driving circuit with the scan start signal or the second output signal,

and wherein the discharging circuit comprises:

a first discharge transistor that discharges the electric charge to the first voltage in response to the third output signal; and

a second discharge transistor that discharges the electric charge to the first voltage in response to a fourth output signal of a last stage.

39. The display apparatus of claim 37, wherein each of the stages further comprises a buffer configured to supply the driving circuit with the scan start signal or the second output signal, and a hold controlling circuit that outputs a hold control signal when the first or the second clock signal applied to the driving circuit is in an active state,

and wherein the holding circuit comprises:

a first hold transistor including a first electrode that receives the first output signal, a control electrode that is electrically connected to the hold controlling circuit to receive the hold control signal, and a second electrode that receives the first voltage;

a second hold transistor including a first electrode that receives the scan start signal or the second output signal, a control electrode that receives the second clock signal, and a second electrode that is electrically connected to a first end of the charging circuit;

a third hold transistor including a first electrode that is electrically connected to the first end of the charging circuit, a control electrode that receives the first clock signal, and a second electrode that receives the first output signal; and

a fourth hold transistor including a first electrode that receives the first output signal, a control electrode that receives the second clock signal, and a second electrode that receives the first voltage.

40. The display apparatus of claim 37, wherein the driving circuit comprises a first driving transistor and a second driving transistor including a first electrode that receives the first or the second clock signal applied to the driving circuit and a second electrode, via which the first output signal is pulled up, and the first driving transistor compensates a capacity of the second driving transistor.

41. The display apparatus of claim 40, wherein a size of the first driving transistor is about five times larger than that of the second driving transistor.

42. The display apparatus of claim 40, wherein the first driving transistor receives the first output signal via one of the scan lines and a first electrode of the first driving transistor so that the second voltage is discharged via a second electrode of the first driving transistor, when a control electrode of the first driving transistor is turned on.

43. The display apparatus of claim 42, wherein the second voltage is higher than the first voltage.