Asymmetrical SRAM device and method of manufacturing the same

• US 7,486,543 B2
• Filed: 03/28/2005
• Issued: 02/03/2009
• Est. Priority Date: 06/12/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Tae-woong, Ahn, Jong-hyon
• Primary Examiner(s): Huynh; Andy
• Assistant Examiner(s): HO, HOANG QUAN TRAN
• Application Number:
  US11/090,160
• Publication Number:
  US 20050275117A1
• Time in Patent Office: 1,408 Days
• Field of Search: None
• US Class Current: 365/156
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

In an asymmetrical SRAM device, and a method of manufacturing the same, the asymmetrical SRAM device includes a semiconductor substrate on which a plurality of unit cell regions are defined, and a plurality of active regions formed in each of the unit cell regions of the semiconductor substrate, wherein the active regions of each unit cell region are a mirror image of active regions of an adjacent one of the plurality of unit cell regions with respect to a boundary line between the adjacent unit cell regions.

Claims

1. An asymmetrical SRAM device, comprising:

a semiconductor substrate on which a plurality of unit cell regions are defined;

a plurality of active regions formed in each of the unit cell regions of the semiconductor substrate;

a first pass transistor region extending into each of four adjacent unit cell regions in a first set of unit cell regions; and

a second NMOS transistor region extending each of four adjacent unit cell regions in a second set of unit cell regions, wherein;

the active regions of each unit cell region are a mirror image of active regions of an adjacent one of the plurality of unit cell regions with respect to a boundary line between the adjacent unit cell regions,

the active regions of each unit cell region include;

a first NMOS active region in which a first NMOS transistor and a first pass transistor are disposed,

a second NMOS active region in which a second NMOS transistor and a second pass transistor are disposed,

a first PMOS active region in which a first PMOS transistor is disposed, and

a second PMOS active region in which a second PMOS transistor is disposed,

the second NMOS transistor has more threshold voltage control ions for high threshold voltage than the first NMOS transistor,

the first pass transistor has more threshold voltage control ions for high threshold voltage than the second pass transistor,

the first PMOS transistor has more threshold voltage control ions for high threshold voltage than the second PMOS transistor,

the first pass transistor region includes a first common region that is common to each of the four adjacent unit cell regions in the first set, the first common region having a first level of voltage control ions,

the second NMOS transistor region includes a second common region that is common to each of the four adjacent unit cell regions in the second set, the second common region having a second level of voltage control ions,

a first pass transistor from each of the four adjacent unit cell regions of the first set is disposed in the first pass transistor region, and

a second NMOS transistor from each of the four adjacent cell regions of the second set is disposed in the second NMOS transistor region.

2. The asymmetrical SRAM device as claimed in claim 1, further comprising, for each unit cell region:

a first gate electrode extended to traverse over the first NMOS active region and the first PMOS active region;

a second gate electrode extended to traverse over the second NMOS active region and the second PMOS active region;

a first word line parallel to the first gate electrode and traversing over the first pass transistor; and

a second word line parallel to the second gate electrode and traversing over the second pass transistor.

3. The asymmetrical SRAM device as claimed in claim 2, further comprising source/drain regions of the MOS transistors respectively formed on the active region on both sides of the first and second gate electrodes and the first and second word lines.

4. The asymmetrical SRAM device as claimed in claim 3, further comprising:

a first metal wiring that electrically connects the first gate electrode and the drain of the second NMOS transistor; and

a second metal wiring that electrically connects the second gate electrode and the drain of the first NMOS transistor.

14. The asymmetrical SRAM device as claimed in claim 1, wherein:

the first pass transistor region overlaps portions of two first NMOS active regions, the two first NMOS active regions belonging to adjacent unit cell regions, and

the second NMOS transistor region overlaps portions of two second NMOS active regions, the two second active regions belonging to adjacent unit cell regions.

15. The asymmetrical SRAM device as claimed in claim 14, wherein the first level of voltage control ions is substantially equal to the second level of voltage control ions.

16. The asymmetrical SRAM device as claimed in claim 14, wherein:

the first NMOS active regions have a third level of voltage control ions, and

the first pass transistor has a level of voltage control ions that is substantially equal to the first level plus the third level.

17. The asymmetrical SRAM device as claimed in claim 16, wherein:

the second NMOS active regions have a fourth level of voltage control ions, and

the second NMOS transistor has a level of voltage control ions that is substantially equal to the second level plus the fourth level.

5. An asymmetrical SRAM device, comprising:

a semiconductor substrate on which a plurality of unit cell regions are defined in a matrix;

a plurality of active regions located in each of the unit cell regions and including a first NMOS active region having a first NMOS transistor and a first pass transistor, a second NMOS active region having a second NMOS transistor and a second pass transistor, a first PMOS active region, and a second PMOS active region;

a gate structure including;

a first gate electrode traversing over the first NMOS active region and the first PMOS active region,

a second gate electrode traversing over the second NMOS active region and the second PMOS active region,

a first word line traversing over the first pass transistor, and

a second word line traversing over the second pass transistor;

a plurality of source and drain regions respectively formed on the active region on both sides of the gate structure to define the first NMOS transistor within the first NMOS active region, the second NMOS transistor within the second NMOS active region, a first PMOS transistor within the first PMOS active region, a second PMOS transistor within the second PMOS active region, the first pass transistor within the first NMOS active region, and the second pass transistor within the second NMOS active region wherein;

the second NMOS transistor has more threshold voltage control ions for high threshold voltage than the first NMOS transistor,

the first pass transistor has more threshold voltage control ions for high threshold voltage than the second pass transistor,

the first PMOS transistor has more threshold voltage control ions for high threshold voltage than the second PMOS transistor,

each unit cell region is a mirror image of an adjacent one of the unit cell regions with respect to a boundary line between the adjacent unit cell regions such that the second NMOS transistor is located adjacent to the boundary line of the unit cell region to face three other second NMOS transistors having more voltage control ions for high threshold voltage in adjacent unit cell regions, the first pass transistor is located adjacent to the boundary line of the unit cell to face three other first pass transistors having more voltage control ions for high threshold voltage in the adjacent unit cell regions, and the first PMOS transistor is located adjacent to the boundary line of the unit cell region to face another first PMOS transistor having more voltage control ions for high threshold voltage in the adjacent unit cell region,

a first pass transistor region surrounds the first pass transistor in the unit cell region as well as the three other first pass transistors in the adjacent unit cell regions, the first pass transistor region including a first common region having a first level of voltage control ions, and

a second NMOS transistor region surrounds the second NMOS transistor in the unit cell region as well as the three other second NMOS transistors in the adjacent unit cell regions, the second NMOS transistor region including a second common region having a second level of voltage control ions.

6. The asymmetrical SRAM device as claimed in claim 5, wherein an end of the second PMOS active region is shifted from a corresponding end of the first PMOS active region by a predetermined distance, thereby overlapping a predetermined portion of the second PMOS active region and an isolation film.

7. The asymmetrical SRAM device as claimed in claim 5, wherein the first and second gate electrodes extend parallel to each other, and the first word line extends parallel to the first gate electrode a predetermined distance apart therefrom, and the second word line extends parallel to the second gate electrode a predetermined distance apart therefrom.

8. The asymmetrical SRAM device as claimed in claim 7, wherein the first gate electrode further extends to overlap a predetermined portion of the second PMOS active region, and the first gate electrode overlaps an end of the second PMOS active region.

9. The asymmetrical SRAM device as claimed in claim 7, wherein the second gate electrode further extends to overlap a predetermined portion of the first PMOS active region, and the second gate electrode overlaps an end of the second PMOS active region.

10. The asymmetrical SRAM device as claimed in claim 5, further comprising:

a first metal wiring that electrically connects the first gate electrode and the drain of the second NMOS transistor; and

a second metal wiring that electrically connects the second gate electrode and the drain of the first NMOS transistor.

18. The asymmetrical SRAM device as claimed in claim 5, wherein:

the first pass transistor region overlaps portions of two first NMOS active regions, the two first NMOS active regions belonging to adjacent unit cell regions, and

the second NMOS transistor region overlaps portions of two second NMOS active regions, the two second active regions belonging to adjacent unit cell regions.

19. The asymmetrical SRAM device as claimed in claim 18, wherein the first level of voltage control ions is substantially equal to the second level of voltage control ions.

20. The asymmetrical SRAM device as claimed in claim 18, wherein:

the first NMOS active regions have a third level of voltage control ions, and

the first pass transistor has a level of voltage control ions that is substantially equal to the first level plus the third level.

21. The asymmetrical SRAM device as claimed in claim 20, wherein:

the second NMOS active regions have a fourth level of voltage control ions, and

the second NMOS transistor has a level of voltage control ions that is substantially equal to the second level plus the fourth level.

11. An asymmetrical SRAM device, comprising:

a plurality of unit cell regions; and

a unit SRAM cell formed in each unit cell region, the unit SRAM cell including;

a first inverter having a first PMOS transistor and a first NMOS transistor,

a second inverter having a second PMOS transistor and a second NMOS transistor, wherein a threshold voltage of the first PMOS transistor is higher than a threshold voltage of the second PMOS transistor, and a threshold voltage of the second NMOS transistor is higher than a threshold voltage of the first NMOS transistor,

a first pass transistor connected to an input of the second inverter, and

a second pass transistor connected to an input of the first inverter, wherein a threshold voltage of the first pass transistor is higher than a threshold voltage of the second pass transistor,

wherein;

the unit SRAM cell is a mirror image of an adjacent unit SRAM cell with respect to a boundary line between adjacent unit SRAM cells,

the first PMOS transistor, the second NMOS transistor, and the first pass transistor are located adjacent to the boundary line of the unit SRAM cell to face another PMOS transistor in an adjacent unit SRAM cell having a threshold voltage higher than a threshold voltage of a second PMOS transistor in the adjacent unit SRAM cell, another second NMOS transistor in an adjacent unit SRAM cell having a threshold voltage higher than a threshold voltage of a first NMOS transistor in the adjacent unit SRAM cell and another first pass transistor in an adjacent unit SRAM cell having a threshold voltage higher than a threshold voltage of a second pass transistor in the adjacent unit SRAM cell,

the first pass transistor, the other first pass transistor, and two additional first pass transistors are disposed in a first pass transistor region, the first pass transistor region including a first common region having a first level of voltage control ions, and

the second NMOS transistor, the other second NMOS transistor, and two additional second NMOS transistors are disposed in a second NMOS transistor region, the second NMOS transistor region including a second common region having a second level of voltage control ions.

12. The asymmetrical SRAM device as claimed in claim 11, wherein the unit SRAM cell comprises a plurality of active regions, on which the transistors are formed,

wherein the plurality of active regions comprises:

a first NMOS active region partially overlapping the first pass transistor region, on which the first NMOS transistor and the first pass transistor are formed;

a second NMOS active region partially overlapping the second NMOS transistor region, on which the second NMOS transistor and the second pass transistor are formed;

a first PMOS active region, on which the first PMOS transistor is formed; and

a second PMOS active region, on which the second PMOS transistor is formed wherein;

each of the first and second NMOS active regions and the first and second PMOS active regions are formed in a bar shape extending in a same direction,

the first and second NMOS active regions are parallel to each other spaced apart by a predetermined distance, and

the first and second PMOS active regions are located between the first and second NMOS active regions.

13. The asymmetrical SRAM device as claimed in claim 12, further comprising:

a first gate electrode extended to traverse over a predetermined portion of the first NMOS active region and a predetermined portion of the first PMOS active region;

a second gate electrode extended to traverse over a predetermined portion of the second NMOS active region and a predetermined portion of the second PMOS active region;

a first word line parallel to the first gate electrode and traversing over a predetermined portion of the first NMOS active region; and

a second word line parallel to the second gate electrode and traversing over a predetermined portion of the second NMOS active region.