Non-volatile memory with managed execution of cached data

• US 7,486,558 B2
• Filed: 05/05/2006
• Issued: 02/03/2009
• Est. Priority Date: 04/01/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Li, Yan
• Primary Examiner(s): Zarabian; Amir
• Assistant Examiner(s): Weinberg; Michael J
• Application Number:
  US11/382,000
• Publication Number:
  US 20070002626A1
• Time in Patent Office: 1,005 Days
• Field of Search: None
• US Class Current: 365/185.12
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/3042 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and circuitry are present for executing current memory operation while other multiple pending memory operations are queued. Furthermore, when certain conditions are satisfied, some of these memory operations are combinable or mergeable for improved efficiency and other benefits. The management of the multiple memory operations is accomplished by the provision of a memory operation queue controlled by a memory operation queue manager. The memory operation queue manager is preferably implemented as a module in the state machine that controls the execution of a memory operation in the memory array.

Claims

1. A non-volatile memory device having addressable pages of memory cells in a core array, comprising:

a set of data latches for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits;

a first-in-first-out queue for incoming memory operations and for outputting the queued memory operations to be executed in the core array;

a set of mergeable conditions when two or more memory operations are mergeable into a combined memory operation, the combined memory operation operating on all data associated with the operations being combined;

a queue manager for accepting an incoming memory operation into the queue whenever there are sufficient data latches available for caching the data associated with the incoming memory operation;

wherein

whenever a memory operation being executed in the core array is mergeable with one or more queued memory operations to be outputted from the queue, said queue manager terminates the memory operation being executed and instead executes a combined memory operation of the mergeable memory operations; and

whenever two or more queued memory operations to be outputted from the queue are mergeable among themselves but not with a memory operation being executed in the core array, said queue manager executes a combined queued memory operation of the mergeable memory operations after the memory operation being executed in the core array has completed.

2. The non-volatile memory device of claim 1, wherein one of the incoming memory operations is a program operation.

3. The non-volatile memory device of claim 2, wherein the data associated with the program operation is a page of binary program data to be programmed.

4. The non-volatile memory device of claim 1, wherein the memory cells individually store binary data.

5. The non-volatile memory device of claim 2, wherein the memory cells individually, store binary data.

6. The non-volatile memory device of claim 3, wherein the memory cells individually store binary data.

7. The non-volatile memory device of claim 1, wherein the memory cells individually store multi-bits of data.

8. The non-volatile memory device of claim 2, wherein the memory cells individually store multi-bits of data.

9. The non-volatile memory device of claim 3, wherein the memory cells individually store multi-bits of data.

10. The non-volatile memory device of claim 9, wherein each of the multi-bits of data in the page of memory cells forms a single bit of data of a corresponding logical page such that there are as many logical pages as there are multi-bits for each page of memory cells.

11. The non-volatile memory device of claim 10, wherein the incoming operation is one of a plurality of program operations each for programming a logical page of data.

12. The non-volatile memory device of claim 11, wherein the set of mergeable conditions includes when the data associated with the memory operations to be merged are from logical pages belonging to the same page of memory cells.

13. The non-volatile memory device of claim 12, wherein the set of mergeable conditions includes when the memory operations to be merged are queued in a predetermined order.

14. The non-volatile memory device of claim 13, wherein the predetermined order is specified by a coding system for the multi-bits memory cell.

15. The non-volatile memory device of any one of claims 7-14, wherein the memory cells each stores two bits of data.

16. The non-volatile memory device of any one of claims 7-14, wherein the memory cells each stores more than two bits of data.

17. The non-volatile memory device of claim 14, wherein:

the coding system is for a 2-bit memory cell having a lower bit and an upper bit; and

the predetermined order is from the lower bit to the upper bit.

18. The non-volatile memory device of claim 17, wherein:

the memory operations to be merged include a program operation on a lower-bit page and a program operation on an upper-bit page.

19. The non-volatile memory device of claim 14, wherein:

the coding system is for a 3-bit memory cell having a lower bit, a middle bit and an upper bit; and

the predetermined order is from the lower bit to the middle bit to the upper bit.

20. The non-volatile memory device of claim 19, wherein:

the memory operations to be merged include a program operation on a lower-bit page and a program operation on a middle-bit page.

21. The non-volatile memory device of claim 19, wherein:

the memory operations to be merged include a program operation on a middle-bit page and a program operation on an upper-bit page.

22. The non-volatile memory device of claim 19, wherein:

the memory operations to be merged include a program operation on a lower-bit page, a program operation on a middle-bit page and a program operation on an upper-bit page.