Sense amplifier circuitry and architecture to write data into and/or read from memory cells

• US 7,486,563 B2
• Filed: 11/05/2007
• Issued: 02/03/2009
• Est. Priority Date: 12/13/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Innovative Silicon ISI SA
• Inventors: Carman, Eric, Waller, William Kenneth
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US11/982,807
• Publication Number:
  US 20080062793A1
• Time in Patent Office: 456 Days
• Field of Search: 365/205, 365/185.21, 365/196, 365/207, 365/189.09, 365/154, 365/210.14
• US Class Current: 365/185.21
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 2211/4013 Memory devices with multiple cells per bit, e.g. twin-cells
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A technique of, and circuitry for sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, sense amplifier circuitry is relatively compact and pitched to the array of memory cells such that a row of data may be read, sampled and/or sensed during a read operation. In this regard, an entire row of memory cells may be accessed and read during one operation which, relative to at least architecture employing multiplexer circuitry, may minimize, enhance and/or improve read latency and read access time, memory cell disturbance and/or simplify the control of the sense amplifier circuitry and access thereof. The sense amplifier circuitry may include write back circuitry to modify or “re-store” the data read, sampled and/or sensed during a read operation and/or a refresh operation in the context of a DRAM array. Moreover, the data that has been read, sampled and/or sensed by the sense amplifier circuitry during a read operation may be modified before being written back to one or more of the memory cells of the selected row of the array of memory cells.

Claims

1. An integrated circuit device comprising:

a bit line having a plurality of memory cells coupled thereto wherein each memory cell includes an electrically floating body transistor comprising;

a source region;

a drain region;

a body region disposed between the source region and the drain region,

wherein the body region is electrically floating; and

a gate disposed over the body region; and

wherein each memory cell includes a plurality of data states including a first data state which corresponds to a first charge in the body region of the transistor and a second data state which corresponds to a second charge in the body region of the transistor;

data sense circuitry, coupled to the bit line, the data sense circuitry including;

a sense amplifier having a plurality of inputs including;

a first input, having a capacitance, to receive a signal, wherein the sense amplifier includes at least one transistor coupled to the bit line to receive the signal on the first input wherein the signal is representative of a data state of a selected memory cell, and wherein the selected memory cell is one of the plurality of memory cells which are coupled to the bit line; and

a second input to receive a reference signal;

circuitry, coupled to the bit line, to (a) write the data state of the selected memory cell or (b) write (i) the data state back into the selected memory cell or (ii) a different data state into the selected memory cell; and

wherein, in operation, the sense amplifier determines the data state of the selected memory cell based on (i) a first voltage developed on the first input wherein the first voltage corresponds to the signal representative of a data state of a selected memory cell and (ii) a second voltage provided to the second input wherein the second voltage corresponds to the reference signal.

2. The integrated circuit device of claim 1 wherein the gate of the first transistor of the sense amplifier is connected to the first input.

3. The integrated circuit device of claim 2 wherein the sense amplifier is a cross-coupled type sense amplifier.

4. The integrated circuit device of claim 1 further including a current mirror circuit coupled between the bit line and the first input.

5. The integrated circuit device of claim 1 further including reference current generation circuitry, coupled to the second input, to generate the reference signal.

6. The integrated circuit device of claim 5 further including a current mirror circuit which is coupled between the second input and the reference current generation circuitry.

7. The integrated circuit device of claim 1 wherein the sense amplifier determines the data state of the selected memory cell based on the voltage developed on the first input provided by:

charging or discharging the capacitance of the first input by a current which is representative of the data state of the selected memory cell.

8. The integrated circuit device of claim 1 further including voltage level shifter circuitry coupled between the circuitry and the sense amplifier.

9. An integrated circuit device comprising:

a bit line having a plurality of memory cells coupled thereto wherein each memorycell includes an electrically floating body transistor comprising;

a source region;

a drain region;

a body region disposed between the source region and the drain region,

wherein the body region is electrically floating; and

a gate disposed over the body region; and

wherein each memory cell includes a plurality of data states including a first data state representative of a first charge In the body region of the transistor and a second data state representative of a second charge in the body region of the transistor;

data sense circuitry, coupled to the bit line, the data sense circuitry including a sense amplifier which includes a plurality of inputs including;

a first input, having a capacitance, to receive a signal, wherein the sense amplifier includes at least one transistor coupled to the bit line to receive the signal on the first input wherein the signal is representative of a data state of a selected memory cell, and wherein the selected memory cell is one of the plurality of memory cells which are coupled to the bit line;

a second input to receive a reference signal; and

a pitch that is substantially the same as a pitch of the bit line; and

wherein, in operation, the sense amplifier determines the data state of the selected memory cell based on;

(i) a first voltage developed on the first input wherein the first voltage corresponds to the signal representative of a data state of a selected memory cell and (ii) a second voltage provided to the second input wherein the second voltage corresponds to the reference signal.

10. The integrated circuit device of claim 9 wherein the gate of the first transistor of the sense amplifier is connected to the first input.

11. The integrated circuit device of claim 9 wherein the sense amplifier is a cross-coupled type sense amplifier.

12. The integrated circuit device of claim 9 further including a current mirror circuit coupled between the bit line and the first input.

13. The integrated circuit device of claim 9 further including reference current generation circuitry, coupled to the second input node, to generate the reference signal.

14. The integrated circuit device of claim 13 further including a current mirror circuit which is coupled between the second input and the reference current generation circuitry.

15. The integrated circuit device of claim 9 wherein the sense amplifier determines the data state of the selected memory cell based on the voltage developed on the first input node provided by:

charging or discharging the capacitance of the first input by a current which is representative of the data state of the selected memory cell.

16. An integrated circuit device comprising:

a bit line having a plurality of memory cells coupled thereto wherein each memory cell includes an electrically floating body transistor including;

a source region;

a drain region;

a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and

a gate disposed over the body region; and

wherein each memory cell includes a plurality of data states including a first data state representative of a first charge in the body region of the transistor and a second data state representative of a second charge in the body region of the transistor;

a sense amplifier including first and second input nodes, each input node having an intrinsic capacitance, wherein the sense amplifier further includes;

a first transistor having first and second regions and a gate, wherein the first region is connected to or forms a part of the first input node, and wherein the first input node is coupled to the bit line to receive a current which is representative of a data state of a selected memory cell, wherein the selected memory cell is one of the plurality of memory cells which are coupled to the bit line; and

a second transistor having first and second regions and a gate, wherein the first region of the second transistor is connected to or forms a part of the second input node, and wherein the second input node receives a reference current; and

reference current generation circuitry, coupled to the second input node of the sense amplifier, to generate a current that is representative of the reference current;

first current mirror circuit having an input which is coupled to the reference generation circuitry and an output which is coupled to the second input node; and

wherein, in operation, the sense amplifier determines the data state of the selected memory cell based on voltages developed on the first and second input nodes.

17. The integrated circuit device of claim 16 wherein:

the gate of the first transistor of the sense amplifier is connected to the second input node and the gate of the second transistor of the sense amplifier is connected to the first input node;

the second region of the first transistor of the sense amplifier is connected to a first reference voltage and the second region of the second transistor of the sense amplifier is connected to the first reference voltage; and

wherein the sense amplifier further includes third and fourth transistors, each having first and second regions and a gate, wherein;

the first regions of the third and fourth transistors are connected and coupled to a second reference voltage;

the second region of the third transistor is connected to or forms a part of the first input node;

the second region of the fourth transistor is connected to or forms a part of the second input node;

the gate of the third transistor is connected to the second input node; and

the gate of the fourth transistor is connected to the first input node.

18. The integrated circuit device of claim 16 further including:

write back circuitry, coupled to the sense amplifier, to restore the data state of the selected memory cell or write a new data state into the selected memory cell; and

voltage level shifter circuitry coupled between the write back circuitry and the sense amplifier.

19. The integrated circuit device of claim 16 further including write back circuitry, coupled to the sense amplifier, to restore the data state of the selected memory cell or write a new data state into the selected memory cell.

20. The integrated circuit device of claim 16 wherein the sense amplifier determines the data state of the selected memory cell based on voltages developed on the first and second input nodes provided by:

charging or discharging the intrinsic capacitance of the first input node by the current which is representative of the data state of the selected memory cell; and

charging or discharging the intrinsic capacitance of the second input node by the reference current.

21. The integrated circuit device of claim 16 wherein the sense amplifier includes a pitch that is substantially the same as a pitch of the bit line.

22. The integrated circuit device of claim 16 further including a second current mirror circuit having an input which is coupled to the bit line and an output which is coupled to the first input node.

23. The integrated circuit device of claim 16 further including write back circuitry, coupled to the first input node of the sense amplifier, to restore the data state of the selected memory cell or write a new date state into the selected memory cell.

24. The integrated circuit device of claim 16 further including voltage level shifter circuitry coupled between the bit line and the sense amplifier.

25. The integrated circuit device of claim 16 wherein the sense amplifier determines the data state of the selected memory cell based, at least in part, on voltages developed on the first and second input nodes provided by charging or discharging the capacitance of the first input node by the current which is representative of the data state of the selected memory cell.