High-performance, superscalar-based computer system with out-of-order instruction execution

• US 7,487,333 B2
• Filed: 11/05/2003
• Issued: 02/03/2009
• Est. Priority Date: 07/08/1991
• Status: Expired due to Fees

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Trang, Quang H, Lentz, Derek J, Nguyen, Le-Trong, Wang, Johannes, Wang, Sze-Shun, Miyayama, Yoshiyuki, Lau, Te-Li, Garg, Sanjiv, Hagiwara, Yasuaki
• Primary Examiner(s): Li; Aimee J
• Application Number:
  US10/700,485
• Publication Number:
  US 20040093485A1
• Time in Patent Office: 1,917 Days
• Field of Search: 712/206, 712/245, 712/239
• US Class Current: 712/206
• CPC Class Codes: G06F 9/30061 Multi-way branch instructions, e.g. CASE
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/327 for interrupts
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 : Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3863 : using multiple copies of the architectural state, e.g. shadow registers
• CPC Class Codes: G06F 9/3865 : using deferred exception handling, e.g. exception flags
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Claims

1. A superscalar microprocessor for processing instructions, the microprocessor comprising:

an instruction fetch unit configured to fetch instructions from an instruction store according to a sequential program order;

a branch prediction circuit configured to provide a branch bias signal indicating whether a conditional branch controlled by a conditional branch instruction is predicted to be taken or not taken;

an instruction buffer coupled to receive fetched instructions from the instruction fetch unit and configured to buffer a plurality of fetched instructions, including an instruction selected according to the branch bias signal;

a plurality of functional units configured to execute instructions, thereby generating result data;

a register file including a plurality of entries configured to store data including result data generated by the plurality of functional units, wherein each of the plurality of entries is accessible by reference to a respective location in the register file;

a resource identifying circuit configured to concurrently identify execution resources for a first one and a second one of a plurality of buffered instructions, wherein the second one of the buffered instructions has a data dependency on the first one of the buffered instructions, thereby making a plurality of instructions concurrently available for issue, wherein the identified execution resources for each of the available instructions includes a functional unit capable of executing the instruction;

a register rename circuit configured to provide references to locations in the register file for logical register references included with the plurality of buffered instructions;

an issue control circuit coupled to the resource identifying circuit and configured to concurrently issue more than one of the available instructions to the functional units for execution, based on availability of the identified execution resources for each instruction and availability of respective operands for each instruction in the referenced locations in the register file, without regard to the sequential program order;

a plurality of data routing paths coupled between the plurality of functional units and the register file and configured to concurrently transfer result data from more than one of the plurality of functional units to the register file; and

bypass control logic coupled to the plurality of data routing paths and configured to distribute result data from a first one of the plurality of functional units as operand data for another one or more of the plurality of functional units via an alternate data path that bypasses the register file, wherein distributing result data via the alternate data path occurs concurrently with transferring result data to the register file.

2. The microprocessor of claim 1, wherein:

the plurality of functional units includes an integer functional unit and a floating-point functional unit; and

the bypass control logic is further configured such that an integer result from the integer functional unit is distributed to the floating-point functional unit via the alternate data path.

3. The microprocessor of claim 1, wherein:

the plurality of functional units includes an integer functional unit and a floating-point functional unit; and

the bypass control logic is further configured such that a floating-point result from the floating-point functional unit is distributed to the integer functional unit via the alternate data path.

4. The microprocessor of claim 1, further comprising:

operand data routing paths coupled between the register file and the functional units and configured to concurrently transfer operand data to more than one of the functional units.

5. The microprocessor of claim 4, wherein the operand data routing paths transfer operand data directly from the register file to the functional units.

6. The microprocessor of claim 1, wherein the register rename circuit is further configured to concurrently provide references to locations in the register file for the first one and the second one of the plurality of the buffered instructions.

7. The microprocessor of claim 1, wherein the logical register references include at least one of a source register reference and a destination register reference.

8. A method for processing instructions in a superscalar microprocessor, the method comprising:

fetching instructions from an instruction store according to a sequential program order;

predicting whether a conditional branch controlled by a conditional branch instruction included in the fetched instructions is taken or not taken;

buffering a plurality of fetched instructions, including an instruction selected according to the prediction, in an instruction buffer;

concurrently identifying execution resources for more than one of a plurality of buffered instructions, the identified execution resources for each of the more than one of the plurality of buffered instructions including a functional unit capable of executing the instruction;

providing references to locations in a register file for logical register references included with the plurality of buffered instructions, wherein the register file includes a plurality of entries, each of the plurality of entries being accessible by reference to a respective location in the register file;

concurrently making available for execution a plurality of instructions for which execution resources are identified and register file location references are provided;

concurrently issuing more than one of the plurality of available instructions for execution by a plurality of functional units, based on availability of the identified execution resources for each available instruction and availability of respective operands for each instruction in the referenced locations in the register file, without regard to the sequential program order;

executing the issued instructions in the plurality of functional units, thereby generating result data;

transferring the result data from the functional units to the register file;

concurrently with said act of transferring, distributing the result data from a first one of the plurality of functional units as operand data for another one or more of the plurality of functional units via a bypass data path that bypasses the register file; and

retiring instructions according to the sequential program order.

9. The method of claim 8, wherein:

the plurality of functional units includes an integer functional unit and a floating point functional unit; and

the act of distributing the result data includes distributing result data from the integer functional unit to the floating point functional unit via the bypass data path.

10. The method of claim 8, wherein:

the plurality of functional units includes an integer functional unit and a floating point functional unit; and

the act of distributing the result data includes distributing result data from the floating point functional unit to the integer functional unit via the bypass data path.

11. The method of claim 8, further comprising:

concurrently transferring operand data from the register file to more than one of the functional units via a plurality of operand data routing paths.

12. The method of claim 11, wherein the operand data routing paths transfer operand data directly from the register file to the functional units.

13. The method of claim 8, wherein the register file includes:

a temporary buffer having a first plurality of entries; and

a retired register array having a second plurality of entries;

and wherein the act of retiring an instruction includes transferring corresponding result data from the temporary buffer to the retired register array.

14. The method of claim 8, wherein concurrently identifying execution resources includes concurrently identifying execution resources for a first one and a second one of the plurality of buffered instructions, wherein the second one of the instructions has a data dependency on the first one of the instructions.

15. The method of claim 8, wherein providing references to locations in the register file includes concurrently providing references to locations in the register file for at least a first one and a second one of the buffered instructions, wherein the second one of the buffered instructions has a data dependency on the first one of the buffered instructions.

16. The method of claim 8, wherein the logical register references include at least one of a source register reference and a destination register reference.

17. A superscalar microprocessor for processing instructions, the microprocessor comprising:

an instruction fetch unit configured to fetch instructions from an instruction store according to a sequential program order;

a branch prediction circuit configured to provide a branch bias signal indicating whether a conditional branch controlled by a conditional branch instruction is predicted to be taken or not taken;

an instruction buffer coupled to receive fetched instructions from the instruction fetch unit and configured to buffer a plurality of fetched instructions, including an instruction selected according to the branch bias signal;

a plurality of functional units configured to execute instructions, thereby generating result data;

a register file including a plurality of entries configured to store data including result data generated by the plurality of functional units, wherein each of the plurality of entries is accessible by reference to a respective location in the register file;

a resource identifying circuit configured to concurrently identify execution resources for a plurality of buffered instructions, thereby making a plurality of instructions concurrently available for issue, wherein the identified execution resources for each of the available instructions includes a functional unit capable of executing the instruction;

a register rename circuit configured to provide references to locations in the register file for logical register references included with the plurality of buffered instructions;

an issue control circuit coupled to the resource identifying circuit and configured to concurrently issue more than one of the available instructions to the functional units for execution, based on availability of the identified execution resources for each instruction and availability of respective operands for each instruction in the referenced locations in the register file, without regard to the sequential program order;

a plurality of data routing paths coupled between the plurality of functional units and the register file and configured to concurrently transfer result data from more than one of the plurality of functional units to the register file;

bypass control logic coupled to the plurality of data routing paths and configured to distribute result data from a first one of the plurality of functional units as operand data for another one or more of the plurality of functional units via an alternate data path that bypasses the register file, wherein distributing result data via the alternate data path occurs concurrently with transferring result data to the register file; and

retirement control logic coupled to the register file and configured to concurrently retire a plurality of instructions according to the sequential program order.

18. The microprocessor of claim 17, wherein the register file includes:

a temporary buffer having a first plurality of entries; and

a retired register array having a second plurality of entries;

and wherein the retirement control logic is further configured such that when an instruction is retired, corresponding result data is transferred from the temporary buffer to the retired register array.

19. A data processing apparatus comprising a super scalar type microprocessor having a plurality of functional units that can execute instructions simultaneously, the microprocessor comprising:

a pre-fetch unit that pre-fetches a plurality of instructions from a memory in preparation for execution by one or more functional units, the plurality of instructions having a predetermined program order;

a branch prediction circuit configured to provide a branch bias signal indicating whether a conditional branch controlled by a conditional branch instruction is predicted to be taken or not taken;

a buffer that holds a plurality of instruction groups, including one or more instruction groups pre-fetched by the pre-fetch unit according to the branch bias signal;

a decoder that simultaneously decodes a plurality of instructions from an instruction group held in the buffer;

a register file including a plurality of registers used in the one or more functional units executing the plurality of decoded instructions, the plurality of registers including a temporary buffer that stores results from execution of instructions outside the predetermined program order;

a dependency check unit that checks for a dependency relation between the plurality of instructions output from the decoder, on the basis of use conditions stored in a register;

an instruction unit that allocates an instruction to a functional unit so that the instruction executes outside the predetermined program order after the instruction is judged by the dependency check unit not to be subject to restriction due to a dependency, wherein when executing instructions outside the predetermined program order, the microprocessor uses the temporary buffer; and

a retirement unit that specifies a register in which to store a result of executing the instruction outside the predetermined program order, wherein the retirement unit retires the instruction in program order after the instruction is completed, wherein when completing the instructions executed outside the predetermined program order, contents of the temporary buffer are written in a corresponding register to retire the instructions.

20. The data processing apparatus of claim 19, further comprising a memory from which the microprocessor accesses data through a system memory bus to allow execution of the instruction group.

21. A superscalar microprocessor for executing instructions, the microprocessor comprising:

an instruction fetch unit configured to fetch instructions from an instruction store according to a sequential program order; and

an instruction execution unit configured to concurrently receive a set of from 1 to a maximum number (N) of instructions from the instruction fetch unit, the instruction execution unit including;

an instruction buffer configured to store instruction information for each instruction received from the instruction fetch unit, wherein the instruction buffer has sufficient capacity to store the instruction information for at least twice the number N of instructions;

a register file comprising a plurality of temporary buffers and a plurality of retired registers, wherein the temporary buffers are arranged in a plurality of groups of temporary buffers, each group of temporary buffers including N of the temporary buffers;

renaming logic configured to concurrently establish an association between each instruction in a set of instructions concurrently received from the instruction fetch unit and a respective one of the temporary buffers in a selected one of the groups of temporary buffers, wherein a position of each instruction within the set of instructions determines which one of the temporary buffers in the selected group of temporary buffers is associated with that instruction;

a plurality of functional units configured to execute instructions, thereby generating result data;

an issue control circuit configured to concurrently issue more than one of the instructions for which instruction information is stored in the instruction buffer to the functional units for execution, the issue control circuit being further configured to issue at least some of the instructions out of the sequential program order;

a plurality of data routing paths coupled between the functional units and the register file and configured to transfer result data from more than one of the functional units to the temporary buffers concurrently; and

retirement control logic coupled to the register file and configured to retire instructions according to the sequential program order, wherein the retirement control logic is further configured to concurrently retire all of the instructions in a set of instructions after all of the instructions in that set of instructions have completed.

22. The superscalar microprocessor of claim 21 wherein the retirement control logic is further configured to concurrently retire all of the instructions in a set of instructions after all of the instructions in the set of instructions have completed and all instructions that precede the set of instructions according to the sequential program order have been retired.

23. The superscalar microprocessor of claim 21 wherein the retirement control logic is further configured such that retiring all of the instructions in a set of instructions includes transferring the result data from the temporary buffers in the group of temporary buffers associated with the set of instructions to selected ones of the retired registers.

24. The superscalar microprocessor of claim 23 wherein the temporary buffers are configured as a FIFO and wherein each group of temporary buffers corresponds to an entry in the FIFO.

25. The superscalar microprocessor of claim 24 wherein the retirement control logic is further configured to advance the FIFO by one group of temporary buffers upon retirement of each set of instructions.

26. The superscalar microprocessor of claim 21 wherein:

the instruction information stored in the instruction buffer includes an identifier of one of the retired registers; and

the retirement control logic is further configured such that retiring all of the instructions in the set of instructions includes transferring the result data for at least one of the instructions in the set of instructions from the temporary buffer associated with that instruction to the one of the retired registers identified by the retired register identifier stored for that instruction.

27. The superscalar microprocessor of claim 21 wherein the instruction buffer is configured as a FIFO and wherein each entry in the FIFO has sufficient capacity to store instruction information for N instructions.

28. The superscalar microprocessor of claim 21 wherein the instruction information stored in the instruction buffer includes information indicating an operation to be performed.

29. The superscalar microprocessor of claim 21 wherein the instruction buffer has the capacity to store the instruction information for exactly twice the number N of instructions.

30. The superscalar microprocessor of claim 21 wherein the number of temporary buffers is equal to the number of instructions for which the instruction buffer has the capacity to store the instruction information.

31. The superscalar microprocessor of claim 21 wherein N is four.

32. The superscalar microprocessor of claim 21 wherein the instruction execution unit further includes:

a decode circuit configured to concurrently decode all of the instructions in a set of instructions concurrently received by the instruction execution unit.

33. The superscalar microprocessor of claim 32 wherein the decode circuit is disposed at a pipeline stage subsequent to a stage at which the instruction information for a set of instructions is stored into the instruction buffer.

34. The superscalar microprocessor of claim 21 further comprising:

bypass control logic coupled to the plurality of data routing paths and configured to supply result data from one of the functional units as operand data for another one of the functional units via an alternate data path that bypasses the register file, wherein supplying the result data via the alternate data path occurs concurrently with transferring the result data to the temporary buffers.

35. The superscalar microprocessor of claim 21 further comprising:

a register rename circuit configured to concurrently identify, for each instruction in a set of instructions concurrently received by the instruction execution unit, a register file entry corresponding to a source of an operand for the instruction.

36. The superscalar microprocessor of claim 35 wherein the register rename circuit is further configured to concurrently identify a register file entry corresponding to a source of an operand for each of a first instruction and a second instruction in a set of instructions wherein the second instruction has a data dependency on the first instruction.

37. The superscalar microprocessor of claim 21 wherein the instruction fetch unit is further configured to provide a new set of instructions to the instruction execution unit in response to a previous set of instructions being retired.

38. The superscalar microprocessor of claim 21 wherein:

the instruction fetch unit includes a branch prediction circuit configured to detect a first conditional branch instruction among the instructions fetched from the instruction store and to predict whether a first conditional branch corresponding to the first conditional branch instruction will be taken or not taken, and

the instruction fetch unit is further configured to deliver instructions subsequent to the first conditional branch instruction to the instruction execution unit based on the prediction.

39. The superscalar microprocessor of claim 38 wherein:

the branch prediction circuit is further configured to detect a second conditional branch instruction among the instructions fetched from the instruction store and to predict, prior to a determination of whether the first conditional branch was correctly predicted, whether a second conditional branch corresponding to the second conditional branch instruction will be taken or not taken, and

the instruction fetch unit is further configured to deliver instructions subsequent to the second conditional branch instruction to the instruction execution unit based on the prediction as to the second conditional branch.

40. The superscalar microprocessor of claim 39 wherein the instruction fetch unit is further configured to continue delivering instructions to the instruction execution unit as long as the instruction buffer is not filled with sets of instructions, regardless of the number of conditional branch instructions that have been previously delivered to the instruction execution unit but not retired.

41. A method for executing instructions in a superscalar microprocessor, the method comprising:

fetching instructions from an instruction store according to a sequential program order;

concurrently delivering a set of from 1 to a maximum number (N) of fetched instructions to an instruction execution unit, wherein the instruction execution unit includes a register file comprising a plurality of temporary buffers and a plurality of retired registers, wherein the temporary buffers are arranged in a plurality of groups of temporary buffers, each group of temporary buffers including N of the temporary buffers;

storing instruction information for each instruction in the set of delivered instructions in an instruction buffer of the instruction execution unit, wherein the instruction buffer has sufficient capacity to store the instruction information for at least twice the number N of instructions;

concurrently establishing an association between each instruction in the set of instructions delivered by the instruction fetch unit and a respective one of the temporary buffers in a selected one of the groups of temporary buffers, wherein a position of each instruction within the set of instructions determines which one of the temporary buffers in the selected group of temporary buffers is associated with that instruction;

concurrently issuing more than one of the instructions for which instruction information is stored in the instruction buffer to a plurality of functional units, wherein at least some of the instructions are issued out of the sequential program order;

executing the issued instructions in the plurality of functional units, thereby generating result data;

concurrently transferring the result data from more than one of the plurality of functional units to the temporary buffers; and

concurrently retiring all of the instructions in the set of instructions after all of the instructions in the set of instructions have completed.

42. The method of claim 41 wherein the act of concurrently retiring is performed after all of the instructions in the set of instructions have completed and all of the instructions that precede the set of instructions in the sequential program order have been retired.

43. The method of claim 41 wherein the act of concurrently retiring all of the instructions in the set of instructions includes transferring the result data from the temporary buffers in the group of temporary buffers associated with the set of instructions to selected ones of the retired registers.

44. The method of claim 43 wherein the temporary buffers are configured as a FIFO and wherein each group of temporary buffers corresponds to an entry in the FIFO, the method further comprising:

advancing the FIFO by one group of temporary buffers after retiring the set of instructions.

45. The method of claim 41 wherein:

the instruction information stored in the instruction buffer includes an identifier of one of the retired registers; and

the act of concurrently retiring all of the instructions in the set of instructions includes transferring the result data for at least one of the instructions in the set of instruction from the temporary buffer associated with the at least one of the instructions to the one of the retired registers identified by the retired register identifier stored for the at least one of the instructions.

46. The method of claim 41 wherein the instruction buffer is configured as a FIFO and wherein each entry in the FIFO has sufficient capacity to store instruction information for N instructions.

47. The method of claim 41 wherein the instruction information stored in the instruction buffer includes information indicating an operation to be performed.

48. The method of claim 41 wherein the instruction buffer has the capacity to store the instruction information for exactly twice the number N of instructions.

49. The method of claim 41 wherein the number of temporary buffers is equal to the number of instructions for which the instruction buffer has the capacity to store the instruction information.

50. The method of claim 41 wherein N is four.

51. The method of claim 41 further comprising:

concurrently decoding all of the instructions in the set of instructions.

52. The method of claim 51 wherein the act of concurrently decoding takes place subsequently to storing the instruction information for the set of instructions into the instruction buffer.

53. The method of claim 41 further comprising:

supplying result data from one of the functional units as operand data for another one of the functional units via an alternate data path that bypasses the register file, wherein supplying the result data via the alternate data path occurs concurrently with transferring the result data to the temporary buffers.

54. The method of claim 41 further comprising:

concurrently identifying, for each instruction in the set of instructions, a register file entry corresponding to a source of an operand for the instruction.

55. The method of claim 54 wherein the act of concurrently identifying is performed regardless of whether one of the instruction in the set of instructions has a data dependency on another of the instructions in the set of instructions.

56. The method of claim 41 further comprising:

delivering a new set of instructions to the instruction execution unit in response to the set of instructions being retired.

57. The method of claim 41 further comprising:

detecting a first conditional branch instruction among the instructions fetched from the instruction store;

predicting whether a first conditional branch corresponding to the first conditional branch instruction will be taken or not taken; and

thereafter fetching one or more additional instructions from the instruction store based on the prediction.

58. The method of claim 57 further comprising:

detecting a second conditional branch instruction among the additional instructions fetched from the instruction store based on the prediction as to the first conditional branch;

predicting, prior to a determination of whether the first conditional branch was correctly predicted, whether a second conditional branch corresponding to the second conditional branch instruction will be taken or not taken; and

fetching one or more further instructions from the instruction store based on the prediction as to the second conditional branch.

59. The method of claim 58 wherein the act of concurrently delivering a set of fetched instructions to the instruction execution unit is repeated as long as the instruction buffer is not filled with sets of instructions, regardless of the number of conditional branch instructions that have been previously delivered to the instruction execution unit but not retired.