Asymmetrical IO method and system

• US 7,487,378 B2
• Filed: 09/19/2005
• Issued: 02/03/2009
• Est. Priority Date: 09/19/2005
• Status: Active Grant

• Current Assignee: ATI Technologies Incorporated (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies Incorporated (Advanced Micro Devices, Inc.)
• Inventors: Macri, Joseph, Gauthier, Claude, Lee, Ming-Ju E., Morein, Stephen, Chen, Lin
• Primary Examiner(s): Connolly; Mark
• Assistant Examiner(s): Abbaszadeh; Jaweed A
• Application Number:
  US11/231,078
• Publication Number:
  US 20070067660A1
• Time in Patent Office: 1,233 Days
• Field of Search: 713/400, 713/600, 713/503, 711/100
• US Class Current: 713/503
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0091 Transmitter details
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence

Abstract

An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

Claims

1. A system, comprising:

a client device configured to transmit data to a host device, receive data from a host device, receive a system timing signal, generate a local client clock signal from the system timing signal, detect a phase relationship between the local client clock signal and the data received from the host device, encode the phase relationship as client clock phase information in a plurality of bits to indicate that the local client clock is early, late, or aligned with respect to the received data, and transmit the client clock phase information to the host device during an electrical turnaround time between read and write operations over a data bus coupling the client device and the host device; and

a host device configured to receive the client clock phase information from the client device, the host device comprising shared data synchronization resources that use the client clock phase information to adjust a host clock for transmitting data to the at least one client device, wherein the shared resources are shared between transmit and receive functions of the host device.

2. The system of claim 1 wherein the shared resources include a control device configured to select one of host clock phase information and client clock phase information to input to a shared phase interpolator.

3. The system of claim 1, wherein the shared resources include a shared phase interpolator that adjusts a phase of the host clock based on one of a transmit phase control signal and a receive phase control signal.

4. The system of claim 3, wherein one of the transmit phase control signal and a receive phase control signal is selected to be input to the shared phase interpolator based on a state of a control signal.

5. The system of claim 4, wherein the control signal indicates whether the host device is transmitting or receiving.

6. The system of claim 1, wherein the host device is further configured to generate a transmit phase control signal from the received client clock phase information.

7. The system of claim 6, wherein the shared synchronization resources include a shared phase interpolator that adjusts the phase of a local host clock to generate an adjusted local host clock based on the transmit phase control signal.

8. The system of claim 7, wherein the adjusted local host clock controls a phase of data transmitted from the host and received by the client.

9. The system of claim 1, wherein the shared resources comprise a control device that controls whether a local host clock is adjusted based on one of local host clock phase information and local client clock phase information.

10. The system of claim 9, wherein the shared resources further comprise a shared signal timing adjustment device that receives the local host clock and one of the local host clock phase information or local client clock phase information and adjusts the local host clock accordingly.

11. The system of claim 1 wherein the host device comprises a host encoder circuit to encode a host phase relationship as local host clock phase information in a plurality of bits to indicate that the local host clock is early, late, or aligned with respect to the data transmitted to the client device.

12. The system of claim 1 wherein the plurality of bits comprises two-bits and wherein the encoding scheme is as follows:

both bits logic low denotes an early client clock phase, both bits logic high denotes a late client clock phase, and both bits at logic different logic levels denotes aligned client clock phase.

13. The system of claim 1 wherein the electrical turnaround time comprises a bus idle period between read and write operations over a data bus coupling the host device to the client device.

14. The system of claim 13 further comprising:

determining whether a sufficient number of clock cycles exists in the bus idle period to transmit the client clock phase information; and

increasing the idle time if an insufficient number of cycles exists in the bus idle period.

15. A host device physical layer, comprising:

a local host clock used to clock data transmitted by the host device to a client device, and to clock data received by the host device from the client device; and

a client phase detection circuit to detect a phase relationship between a local client clock signal and the data transmitted by the host device,

a first encoder circuit to encode a first phase relationship as client clock phase information in a plurality of bits to indicate that the local client clock is early, late, or aligned with respect to the data transmitted by the host device,

a second encoder circuit to encode a second phase relationship as local host clock phase information in a plurality of bits to indicate that the local host clock is early, late, or aligned with respect to the data transmitted to the client device;

an interface configured to receive the client clock phase information during an electrical turnaround time between read and write operations between the client device and the host device; and

a clock adjustment circuit configurable to adjust the local host clock based on one of the local host clock phase information and the local client clock phase information.

16. The host device of claim 15, further comprising a control device that determines whether the local host clock is adjusted based on one of local host clock phase information and local client clock phase information, wherein the control device receives information regarding whether the host device is transmitting data or receiving data.

17. The host device of claim 15, further comprising:

transmit phase control logic configured to receive the local client clock phase information and to generate a transmit phase control signal; and

receive phase control logic configured to receive the local host clock phase information and to generate a receive phase control signal.

18. The host device of claim 17, wherein the clock adjustment circuit receives the local host clock signal and one of the transmit phase control signal and the receive phase control signal and adjusts the local host clock signal accordingly by decoding the encoded phase information from one of the first encoder circuit or the second encoder circuit.

19. An input/output (IO) method, comprising:

determining whether a host device is transmitting data to or receiving data from a client device over a data bus;

detecting a phase relationship between a local client clock signal and the data transmitted by the host device to the client device;

encoding a first phase relationship as client clock phase information in a plurality of bits to indicate that the local client clock is early, late, or aligned with respect to the data transmitted by the host device;

encoding a second phase relationship as local host clock phase information in a plurality of bits to indicate that the local host clock is early, late, or aligned with respect to the data transmitted to the client device;

transmitting the client clock phase information during an electrical turnaround time on the data bus between read and write operations of the client device and the host device; and

based on whether a host device is transmitting or receiving, adjusting a phase of a local host clock using shared host resources in response to one of the local host clock phase information and the local client clock phase information.

20. The method of claim 19, further comprising receiving the local host clock phase information in host transmit phase control logic and generating a transmit phase control signal.

21. The method of claim 20, further comprising receiving the local client clock information in host receive phase control logic and generating a receive phase control signal.

22. The method of claim 21, further comprising selecting one of the transmit phase control signal and the receive phase control signal to input to a shared phase interpolator to adjust the phase of the local host clock.

23. The method of claim 19, further comprising selectively enabling and disabling adjusting the phase of the local host clock.

24. The method of claim 19, further comprising:

adjusting the phase of the local host clock to receive data when adjustment is based on the local host clock phase information; and

adjusting the phase of the local host clock to transmit data when adjustment is based on the local client clock phase information.