Multithreaded microprocessor with register allocation based on number of active threads

• US 7,487,505 B2
• Filed: 08/05/2002
• Issued: 02/03/2009
• Est. Priority Date: 08/27/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bernstein, Debra, Rosenbluth, Mark B., Wolrich, Gilbert
• Primary Examiner(s): An; Meng-Ai
• Assistant Examiner(s): WU, QING YUAN
• Application Number:
  US10/212,945
• Publication Number:
  US 20030041228A1
• Time in Patent Office: 2,374 Days
• Field of Search: 712/23, 712/220, 712/1, 718/102, 718/104, 718107-108, 711 1- 6
• US Class Current: 718/104
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A mechanism in a multithreaded processor to allocate resources based on configuration information indicating how many threads are in use.

Claims

1. A computer implemented method for dynamically partitioning registers to threads currently in use, the method comprising:

determining a number of threads that are currently executing in a multithreaded processor, and storing an indication of said number of threads that are in use, as a context indication; and

allocating a number of registers within said multithreaded processor based on said context indication, said allocating based on a first number of threads and a second number of threads greater than said first number of threads, and allocating such that for said first number of threads, the registers are grouped into a first grouping of registers with groups having a first number of registers per group, and for said second number of threads, the registers are grouped into a second grouping of registers, where said second grouping of registers has half the number of registers per group as compared with said first grouping of registers, but has double the number of groups as compared with said first grouping of registers.

2. The method of claim 1, wherein the storing comprises storing at least one configuration bit in a control and status register.

3. The method of claim 1, the allocating comprising allocating the number of registers in a general purpose register file which includes an address decode portion and a multiplexor coupled to the address decode portion, the multiplexor to receive a thread number and a register number as inputs and to select bits of the thread number and the register number based on the context indication to form an address corresponding to one of the registers.

4. The method of claim 3 wherein the context indication indicates selection of all but the least signification bit of the thread number and all bits of the register number.

5. The method of claim 3 wherein the context indication indicates selection of all but the most significant bit of the register number and all bits of the thread number.

6. The method of claim 3 wherein the selected bits of the register number form a thread-relative register number.

7. A method as in claim 1, wherein said storing uses a single-bit context field within a context enable register, and wherein the single-bit context field indicates, in a first state, that more than a preselected number of threads are in use and, in a second state, indicates that the number of threads in use is less than or equal to the preselected number of threads.

8. A processor configured to dynamically partition registers to threads currently in use, the processor comprising:

a plurality of registers;

a storage location, which stores an indication of a number of threads that are currently executing in the processor reflecting the number of threads that are in use; and

a resource selector, which allocates said registers among said threads based on the indication of the number of threads that are in use, wherein said registers are grouped into X regions, each of the X regions having Y registers grouped therein, and when more than a preselected number of threads are in use, X is doubled and Y is halved.

9. The processor of claim 8, wherein the indication of the number of threads that are in use is a single bit, which in a first state indicates that more than the preselected number of threads are in use and in a second state indicates that the number of threads in use is less than or equal to the preselected number.

10. The processor of claim 9, further comprising a control and status register comprising the storage location.

11. The processor of claim 9, wherein the plurality of registers comprises a general purpose register file which includes an address decode portion, and the resource selector is a multiplexor coupled to the address decode portion, the multiplexor to receive a thread number and a register number as inputs and to select bits of the thread number and the register number based on the indication of the number of threads that are in use to form an address corresponding to one of the registers.

12. The processor of claim 11 wherein the indication of the number of threads that are in use indicates selection of all but the least signification bit of the thread number and all bits of the register number.

13. The processor of claim 11 wherein the indication of the number of threads that are in use indicates selection of all but the most significant bit of the register number and all bits of the thread number.

14. The processor of claim 11 wherein the selected bits of the register number form a thread-relative register number.

15. A system for dynamically partitioning registers to threads currently in use, the system comprising:

a network device;

a memory system; and

a processor comprising;

a plurality of registers,

a storage location, which stores an indication of a number of threads that are currently executing in the processor reflecting the number of threads that are in use, and

a resource selector, which allocates said registers among said threads based on the indication of the number of threads that are in use, wherein said registers are grouped into X regions, each of the X regions having Y registers grouped therein, and when more than a preselected number of threads are in use, X is doubled and Y is halved.

16. The system of claim 15, wherein the indication of the number of threads that are in use is a single bit, which in a first state indicates that more than the preselected number of threads are in use and in a second state indicates that the number of threads in use is less than or equal to the preselected number.

17. The system of claim 16, the processor further comprising a control and status register comprising the storage location.

18. The system of claim 16, wherein the plurality of registers comprises a general purpose register file which includes an address decode portion, and the resource selector is a multiplexor coupled to the address decode portion, the multiplexor to receive a thread number and a register number as inputs and to select bits of the thread number and the register number based on the indication of the number of threads that are in use to form an address corresponding to one of the registers.

19. The system of claim 18 wherein the indication of the number of threads that are in use indicates selection of all but the least signification bit of the thread number and all bits of the register number.

20. The system of claim 18 wherein the indication of the number of threads that are in use indicates selection of all but the most significant bit of the register number and all bits of the thread number.

21. The system of claim 18 wherein the selected bits of the register number form a thread-relative register number.