Intrusion detection using a network processor and a parallel pattern detection engine

• US 7,487,542 B2
• Filed: 01/14/2004
• Issued: 02/03/2009
• Est. Priority Date: 01/14/2004
• Status: Expired due to Fees

• Current Assignee: Trend Micro Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Jeffries, Clark D., Sabhikhi, Ravinder K., Slyfield, Jan M., Boulanger, Marc A., Kravec, Kerry A., Tannhof, Pascal R., Kinard, C. Marcel, Saidi, Ali G.
• Primary Examiner(s): Kincaid, Kristine
• Assistant Examiner(s): Schmidt, Kari L
• Application Number:
  US10/756,904
• Publication Number:
  US 20050154916A1
• Time in Patent Office: 1,847 Days
• Field of Search: 726/4, 726 22- 24, 713/150, 713/153, 713189-194, 717168-173, 717174-178, 710/1, 710/33, 705 51- 54, 705/405
• US Class Current: 726/23
• CPC Class Codes: H04L 63/1416 Event detection, e.g. attack signature detection
• CPC Class Codes: H04L 63/1441 Countermeasures against malicious traffic countermeasures against attacks on cryptographic mechanisms H04L9/002

Abstract

An intrusion detection system (IDS) comprises a network processor (NP) coupled to a memory unit for storing programs and data. The NP is also coupled to one or more parallel pattern detection engines (PPDE) which provide high speed parallel detection of patterns in an input data stream. Each PPDE comprises many processing units (PUs) each designed to store intrusion signatures as a sequence of data with selected operation codes. The PUs have configuration registers for selecting modes of pattern recognition. Each PU compares a byte at each clock cycle. If a sequence of bytes from the input pattern match a stored pattern, the identification of the PU detecting the pattern is outputted with any applicable comparison data. By storing intrusion signatures in many parallel PUs, the IDS can process network data at the NP processing speed. PUs may be cascaded to increase intrusion coverage or to detect long intrusion signatures.

Claims

1. A method for rapid intrusion detection for network communication comprising the steps of:

receiving packets of network data in a network processor coupled to a network fabric;

forwarding routed network data to the network fabric;

coupling selected data from the network data to a parallel pattern detection engine (PPDE), for comparing the selected data in parallel to M sequences of pattern data stored in the PPDE and generating a match output signal when at least one of the M sequences of pattern data compares to a portion of the selected data;

storing N intrusion signatures in the M PUs sequences of pattern data with corresponding identification (ID) data used to identify which of the N intrusion signatures is detected;

storing action code indicating action to take in response to detecting a particular one of the N intrusion signatures;

analyzing the packets of network data for validity thereby generating valid packets of network data as the selected data;

comparing the selected data to the store N intrusion signatures and generating, at network data speed, a pattern compare signal and particular ID data when a particular one of the N intrusion signatures is detected; and

executing the action code corresponding to the particular one of the N intrusion signatures detected;

wherein the PPDE comprises;

an input/output (I/O) interface for coupling data into and out of the PPDE;

M processing units (PUs), each of the M PUs having compare circuitry for comparing each of the sequence of input data to pattern data stored in each of the M PUs and generating a compare output, wherein an address pointer selecting the pattern data in each of the M PUs is modified in response to a logic state of the compare output and an operation code stored with the pattern data;

an input bus for coupling the sequence of input data to each of the M PUs in parallel;

an output bus coupled to the I/O interface for sending output data to the I/O interface;

control circuitry coupled to the I/O interface and coupling control data on a control data bus and identification (ID) on an ID bus to each of the M processing units; and

ID selection circuitry for selecting a match ID from ID data identifying the M PUs in response to a pattern match signal and match mode data, wherein the match ID and match data corresponding to the match ID are saved in a temporary register as the output data.

2. The method of claim 1, wherein the PPDE further comprises cascade circuitry coupled from each of the M PUs to one or more adjacent PUs within the M PUs for selectively coupling chain data between one or more groups of two or more adjacent Pus selected from the M Pus in response to the control data.